Senior ASIC STA Engineer — SoC Timing & Closure

Apple, Inc.; Cupertino (CA); On-site; USD 185,000 - 325,000; Full time

Job summary

Apple in Cupertino seeks an ASIC STA Engineer to own timing closure and verification across the SOC. You will collaborate with multiple SOC teams to develop timing constraints and drive robust, high‑quality IP delivery for leading mobile silicon.

A Bachelor's degree with substantial experience is required; familiarity with Primetime and Synopsys tools is preferred. The role offers strong compensation, benefits, and stock programs with the chance to impact Apple’s next generation SoCs.

Qualifications

• Bachelor's degree required; 10+ years of experience preferred.
• Strong fundamentals in digital design and timing concepts.
• Experience with STA tools and front-end flows is desirable.

Responsibilities

• Own full chip and block timing closure across SOC projects.
• Develop and maintain timing verification methodology and flows.
• Generate block and full chip timing constraints and resolve timing issues.

Skills

Digital design

Scripting TCL

Perl scripting

Timing concepts

Communication across teams

Education

Bachelor's Degree

Tools

Primetime

Galaxy Constraint Analyzer

Synthesis

Job description

Apple in Cupertino seeks an ASIC STA Engineer to own timing closure and verification across the SOC. You will collaborate with multiple SOC teams to develop timing constraints and drive robust, high‑quality IP delivery for leading mobile silicon.

A Bachelor's degree with substantial experience is required; familiarity with Primetime and Synopsys tools is preferred. The role offers strong compensation, benefits, and stock programs with the chance to impact Apple’s next generation SoCs.