Timing Design Engineer: High-Impact PHY/SoC Timing & Equity

Apple; Madison (WI); On-site; USD 139,000 - 257,000; Full time

Benefits offered by this job

Stock purchase plan

Health and dental insurance

Tuition reimbursement

Job summary

Apple is seeking a Timing Design Engineer in Madison to lead static timing analyses and closure on high‑performance PHY/SOC blocks. You will collaborate with RTL, CAD, and layout teams to deliver timing‑driven designs and implement ECOs to fix issues, ensuring power and performance targets are met.

The role focuses on timing closure, physical design coordination, and contributing to next‑generation Apple products. BS degree and 3+ years of relevant experience required.

Qualifications

• Bachelor's degree in a technical discipline required.
• At least 3 years of relevant timing design experience.
• Experience with timing closures on high‑performance PHY or SOC blocks.

Responsibilities

• Create block‑level static timing constraints.
• Close timing on critical blocks with RTL and PD teams.
• Create and approve timing closure rules for power and performance.
• Perform timing optimization and approve design for functionality.
• Produce and implement ECOs to fix timing issues.
• Run timing validation at chip/block level and guide engineers to fixes.
• Assist in CAD and physical design processes for right-by development.

Skills

Timing closures

Verilog

RTL/PD collaboration

STA requirements

SoC engineering

HDL understanding

Timing analysis tools

Education

BS degree

Tools

Verilog

Job description

Apple is seeking a Timing Design Engineer in Madison to lead static timing analyses and closure on high‑performance PHY/SOC blocks. You will collaborate with RTL, CAD, and layout teams to deliver timing‑driven designs and implement ECOs to fix issues, ensuring power and performance targets are met.

The role focuses on timing closure, physical design coordination, and contributing to next‑generation Apple products. BS degree and 3+ years of relevant experience required.