SoC STA/Timing Engineer — Timing Closure & Tapeout

Apple Inc.; San Diego (CA); Hybrid; USD 175,000 - 309,000; Full time

Job summary

Apple Inc. is seeking a SoC Physical Design Engineer focused on STA/Timing to drive timing closure from netlist to tapeout in a high-performance SOC environment.

You will collaborate with design and PD teams to optimize constraints and implement robust timing methodologies. The role requires strong experience in large-scale STA, sub-micron technologies, and Perl/TCL scripting, with a BS and 10+ years in the field.

Qualifications

• BS degree with 10+ years of relevant industry experience.
• Experience with large design STA and Timing Closure.
• Programming skills with Perl and TCL.

Responsibilities

• Work with design teams to understand and debug constraints and facilitate logic changes to improve timing.
• Work with the Physical Design team, highlighting issues and best practices.
• Help create timing ECO’s for project tapeout.
• Create and maintain scripts and methodologies for analysis and runs.
• Create documentation and help with guidelines/specs.
• Deep analysis of timing paths to identify key issues.
• Implement timing infrastructure.

Skills

Perl

TCL

STA

Timing Closure

Education

Bachelor's degree

Job description

Apple Inc. is seeking a SoC Physical Design Engineer focused on STA/Timing to drive timing closure from netlist to tapeout in a high-performance SOC environment.

You will collaborate with design and PD teams to optimize constraints and implement robust timing methodologies. The role requires strong experience in large-scale STA, sub-micron technologies, and Perl/TCL scripting, with a BS and 10+ years in the field.