STA CAD Engineer — SoC Timing & Flow Innovator

Apple, Inc.; Jackson (TN); On-site; USD 150,000 - 278,000; Full time

Benefits offered by this job

Medical and dental coverage

Employee stock purchase plan

Relocation assistance

Discretionary bonuses or commissions

Job summary

Apple, Inc. in Tennessee is seeking a seasoned STA CAD engineer to enhance timing analysis across next-generation Apple Silicon SoCs. You will own static timing methodologies and drive flows for first-time right silicon, collaborating closely with design teams.

The role requires a BS with 3+ years, strong knowledge of STA tools, Python/Tcl scripting, and solid communication. Base pay and relocation may apply; comprehensive benefits provided.

Qualifications

• Experience with static timing analysis tools and flows.
• Proficiency in Python and Tcl scripting.
• Knowledge of STA for large high-performance SoCs.
• Understanding of noise, cross-talk, variation and timing margins.
• Knowledge of timing/SDC constraints; hands-on validation is a plus.
• Excellent communication to explain issues and drive resolutions.

Responsibilities

• Develop, maintain, and improve gate-level STA flows for Apple silicon designs.
• Collaborate with design teams to debug constraints, flow scripts, and timing closure.
• Drive STA methodology updates to boost efficiency and timing correlation.
• Create and maintain timing analysis and power-reduction scripts and methods.
• Support methodologies, tools, and flows for timing constraint verification across teams.
• Analyze timing paths to identify issues and assist post-silicon timing debug.
• Coordinate with EDA vendors to adopt new capabilities.

Skills

STA tools

Python scripting

Tcl scripting

SoC timing

Noise effects

Timing margins

SDC constraints

Strong communicator

Education

BS degree in EE/CS

Job description

Apple, Inc. in Tennessee is seeking a seasoned STA CAD engineer to enhance timing analysis across next-generation Apple Silicon SoCs. You will own static timing methodologies and drive flows for first-time right silicon, collaborating closely with design teams.

The role requires a BS with 3+ years, strong knowledge of STA tools, Python/Tcl scripting, and solid communication. Base pay and relocation may apply; comprehensive benefits provided.