CPU Design Timing Engineer

Apple Inc.; Beaverton (OR); On-site; USD 130,000 - 160,000; Full time

Job summary

A leading technology company in Beaverton, Oregon, is seeking a CPU Design Timing Engineer to take responsibility for timing closure and collaborate with teams on timing changes. Candidates should have a minimum of a Bachelor's degree and 10 or more years of relevant experience, particularly in static timing analysis tools such as PrimeTime and knowledge of noise analysis, scripting, and variation modeling. Join this company that values diversity and equal opportunity.

Qualifications

• Minimum BS and 10+ years of relevant experience.
• Experience with static timing analysis tools such as PrimeTime or Tempus.
• Experience with timing analysis with multiple clock and power domains.

Responsibilities

• Work with the CAD team to develop the timing flow for the project.
• Collaborate with micro-architects and engineers to drive timing closure.

Skills

Static timing analysis tools (PrimeTime, Tempus)

TCL scripting

Perl or Python

Noise analysis

Variation modeling

SDC command usage

Education

Bachelor's degree

Job description

In this role, you will be responsible for all aspects of timing including working with the implementation and RTL teams on timing changes, helping with construction/modify timing flows, timing analysis, and timing closure.

Description

As the CPU Design Timing Engineer, you will be responsible for the timing closure of the project. Responsibilities include but are not limited to:

• Working with the CAD team to develop the timing flow that will be used on the project, including scripting to improve analysis flows and engineer efficiency.
• Work extensively with CPU micro-architects and Implementation engineers to drive timing closure for the CPU.

Minimum Qualifications

• Minimum BS and 10+ years of relevant experience
• Experience with a static timing analysis tool such as PrimeTime® or Tempus®
• Experience with timing analysis with multiple clock and power domains, noise analysis, and fixing noise in designs
• Experience with variation modeling
• Experience with TCL and either Perl or Python
• Experience with SDC command usage including clock definitions, timing exceptions, and IO constraints

Preferred Qualifications

• Prior experience performing timing analysis in high speed digital designs such as CPUs or other similar designs
• Understanding of physical design tools and methodology including logic synthesis, PnR, parasitic extraction, logic equivalence
• Understanding of deep sub-micron technologies and scaling trends
• Working knowledge of CPU microarchitecture including common fundamental timing paths
• Working knowledge of clock-domain crossing and reset-domain crossing
• Experience with RTL modeling and assertion based verification is a plus
• Possess data parsing, analysis and representation/plotting skills

Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant.