Engineer Job Apple Boston

Apple; Boston (MA); On-site; USD 57,308,160 - 85,962,240; Full time

Job summary

Apple in Boston is seeking a STA Engineer to drive timing analysis for edge IP and collaborate with SOC teams on IP design tasks. You will own timing for full chips and blocks, updating models to ensure timing closure while focusing on high performance and low power within the Apple SoC family.

The role requires a Bachelor’s degree and at least 2 years of ASIC timing experience, with hands-on skills in TCL, Perl, and Synopsys GCA. On-site work in Boston, MA is expected.

Qualifications

• Minimum 2 years of experience in ASIC timing analysis and design.
• Proficient in ASIC timing concepts and design methodologies.
• Experience with design timing tools and workflows.

Responsibilities

• Improve edge IP timing and coordinate with SOC teams.
• Collaborate with SOC teams to execute design and timing tasks for IP.
• Own timing for full chip and block level; update timing models.
• Work on SoC contributions focusing on high performance, low power.
• Collaborate to resolve complex timing issues for large SoC blocks.

Skills

ASIC timing concepts

Coordination

Front-end instruments

Timing models

Education

Bachelor’s degree

Tools

TCL

Perl

Synopsys GCA

Job description

Job Overview

Title: STA Engineer. Company: Apple, Location: Boston, USA. Salary: $20-30 per hour. Education: Bachelor’s degree.

Responsibilities

• Drive edge IP improvement and coordinate with various SOC teams.
• Collaborate with SOC teams to execute design and conflict tasks for the unparalleled IP expectations.
• Own timing for full chip and block level, maintain and update timing models and design.
• Work on Apple SoC contributions focusing on sub‑micron, high‑performance, low‑power applications.
• Collaborate with multiple groups to resolve complex timing issues for large SoC blocks.

Qualifications

• Strong fundamentals in the space of Modernized plan.
• Self‑starter and particularly enthusiastic.
• Competent in coordinating vernaculars (TCL and Perl).
• Experience with ASIC design timing thoughts.
• Transparency in STA gadgets (Afternoon) is at least an.
• Experience with front end instruments and approaches, for instance, Mix, Reasoning fairness checks.
• Shared trait in Basic assessment and investigate, using industry standard devices like Synopsys GCA (World Constraint Analyzer) is appealing yet not required.
• Data on timing corners/modes, process assortments and sign uprightness related issues is at least an.
• Ability to commnicate in a perfect world across each and every inside pack.

Experience

Minimum 2 years of experience in ASIC timing analysis and design.