Custom Logic & STA Engineer - Analog/Mixed-Signal

Apple, Inc.; Sunnyvale (CA); On-site; USD 129,000 - 225,000; Full time

Job summary

Apple, Inc. in Sunnyvale, CA is seeking a self-motivated engineer for the role of Custom Logic Design and STA engineer on the Analog/Mixed Signal Design team.

You will perform timing analysis on custom design circuits and deliver timing views to integration teams while developing custom logic in analog/mixed-signal blocks. You will collaborate with RTL and design teams, assist verification and DFT, and help CAD establish robust timing verification methodologies.

Qualifications

• Bachelor's degree required.
• Understanding of timing analysis concepts (setup/hold, timing constraints, etc.).
• Experience in timing analysis/verification in high-speed designs (SerDes, ADC).
• Knowledge of mixed-signal design techniques.
• Proven track record delivering silicon IPs with design and verification.
• Proficiency in circuit modeling and simulation (SPICE).

Responsibilities

• Custom design timing closure ownership throughout the project cycle.
• Develop and implement STA constraints from specs.
• Perform block- and chip-level static timing and noise analysis.
• Design and characterize transistor- and gate-level mixed-signal circuits.
• Collaborate with RTL and design teams on timing changes and robust designs.
• Assist design verification and DFT teams to debug issues.
• Assist CAD in developing timing verification methodologies.

Skills

Timing analysis

SerDes

Mixed-signal design

SPICE modeling

Scripting

Education

Bachelor's degree

Master’s Degree

Tools

NanoTime

PrimeTime

Tempus

Job description

Apple, Inc. in Sunnyvale, CA is seeking a self-motivated engineer for the role of Custom Logic Design and STA engineer on the Analog/Mixed Signal Design team.

You will perform timing analysis on custom design circuits and deliver timing views to integration teams while developing custom logic in analog/mixed-signal blocks. You will collaborate with RTL and design teams, assist verification and DFT, and help CAD establish robust timing verification methodologies.