Technical Lead, Digital Design & SoC Bring‑Up

Astera Labs; San Jose (CA); On-site; USD 160,000 - 200,000; Full time

Job summary

Astera Labs is seeking a Technical Lead Digital Design Engineer to drive RTL implementation for high-performance connectivity SoCs. You will work on micro-architecture to silicon bring-up, collaborating with verification, PD, and DFT teams to deliver robust designs.

The role emphasizes timing closure, design-for-test, and automation, with senior engineers providing guidance. Relevant experience in Server/Storage/Networking markets is expected.

Qualifications

• Bachelor’s degree in electrical engineering or equivalent.
• 5+ years of experience developing SoC/silicon products in Server, Storage, and/or Networking markets.
• Expertise in RTL coding with SystemVerilog and synthesis with Synopsys or Cadence.
• Experience with high-speed design in advanced technology nodes and timing closure.
• Knowledge of functional and formal verification at block and chip level.

Responsibilities

• Own the RTL implementation of complex digital designs from micro-architecture through sign-off.
• Collaborate with verification teams to review test plans and debug issues.
• Support efforts to achieve timing closure and implement DFT features.
• Scripting and automation for ASIC methodology improvement.
• Accountable for design quality with senior engineer support.

Skills

SystemVerilog

Python

Timing analysis

CDC/RDC

UVM verification

Embedded firmware

Education

Bachelor’s degree in electrical engineering or equivalent

Tools

Synopsys

Cadence

CAD automation

Job description

Astera Labs is seeking a Technical Lead Digital Design Engineer to drive RTL implementation for high-performance connectivity SoCs. You will work on micro-architecture to silicon bring-up, collaborating with verification, PD, and DFT teams to deliver robust designs.

The role emphasizes timing closure, design-for-test, and automation, with senior engineers providing guidance. Relevant experience in Server/Storage/Networking markets is expected.