Tech Lead - AI Connectivity Silicon Design

Astera Labs; San Jose (CA); On-site; USD 133,000 - 185,000; Full time

Benefits offered by this job

Discretionary bonus

Incentives and benefits

Job summary

Astera Labs is seeking a Tech Lead Design Engineer to architect and deliver connectivity silicon powering AI clusters. You will own RTL design for assigned blocks from microarchitecture through synthesis, and drive high-quality design flows.

This high-impact role requires collaboration with architecture, verification, DFT, and physical design to move features from spec to silicon and ensure tapeout readiness.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or related field.
• 5+ years of digital design experience, including at least one full chip from spec to tapeout.
• Strong proficiency in Verilog/SystemVerilog, RTL coding, and synthesis flows.
• Hands-on experience with timing closure, CDC, lint, and low-power design techniques.
• Solid understanding of high-speed serial interfaces (PCIe, Ethernet, or similar) and SoC integration.

Responsibilities

• Own RTL design for assigned blocks from microarchitecture through synthesis sign-off.
• Develop high-quality, synthesizable Verilog/SystemVerilog with strong attention to PPA.
• Drive design reviews, lint, CDC, and timing closure activities to silicon-ready quality.
• Partner with architecture to translate specifications into implementation-ready microarchitecture.
• Collaborate with verification on testplans, coverage closure, and bug triage.
• Work with DFT and physical design teams on scan, BIST, floorplanning, and timing closure.
• Mentor junior engineers and contribute to design methodology, scripts, and best practices.
• Debug complex pre-silicon and post-silicon issues across RTL, gate-level, and emulation environments.
• Drive structured, data-driven design decisions in support of aggressive tapeout schedules.

Skills

RTL design

Verilog/SystemVerilog

Synthesis flows

Timing closure

High-speed interfaces

SoC integration

Education

Bachelor's degree in Electrical/Computer Engineering

Tools

Verilog

Job description

Astera Labs is seeking a Tech Lead Design Engineer to architect and deliver connectivity silicon powering AI clusters. You will own RTL design for assigned blocks from microarchitecture through synthesis, and drive high-quality design flows.

This high-impact role requires collaboration with architecture, verification, DFT, and physical design to move features from spec to silicon and ensure tapeout readiness.