Tech Lead, Verification Engineering – High‑Speed Connectivity

Astera Labs; San Jose (CA); On-site; USD 176,000 - 195,000; Full time

Benefits offered by this job

Discretionary bonus

Job summary

Astera Labs in San Jose, CA is seeking an experienced Tech Lead Engineer, Design Verification to define and deliver robust verification for next‑generation connectivity silicon enabling rack‑scale AI infrastructure.

You will partner with RTL, architecture, firmware, and post‑silicon teams to build verification strategies for high‑ bandwidth protocols and drive coverage closure from planning through silicon readiness.

Qualifications

• Bachelor’s degree in Electrical/Computer Engineering or related field.
• 5–8 years in design verification for complex ASICs/SoCs.
• Hands-on with SystemVerilog and UVM environments.
• Experience building verification plans, testbenches, assertions, and coverage.
• Familiar with simulation, waveform-debug, regression, and coverage tools.
• Strong leadership, debugging, and collaboration in rapid development.

Responsibilities

• Define verification strategy and planning for complex connectivity silicon.
• Develop block- and subsystem-level verification plans from specs.
• Create test scenarios, coverage models, checkers, and scoreboards.
• Lead environment development with UVM-based testbenches and agents.
• Drive regression, coverage closure, and silicon readiness milestones.
• Collaborate with RTL/firmware teams to refine interfaces and observability.
• Communicate status and risks to stakeholders and leadership.

Skills

SystemVerilog

UVM

testbench development

coverage models

debugging

leadership

verification strategies

Education

Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related technical field

Master’s degree in Electrical Engineering, Computer Engineering, or a related field

Tools

Simulation tools

Waveform debugging

Regression tools

Coverage tools

Job description

Astera Labs in San Jose, CA is seeking an experienced Tech Lead Engineer, Design Verification to define and deliver robust verification for next‑generation connectivity silicon enabling rack‑scale AI infrastructure.

You will partner with RTL, architecture, firmware, and post‑silicon teams to build verification strategies for high‑ bandwidth protocols and drive coverage closure from planning through silicon readiness.