Tech Lead Engineer - Front-End Digital ASIC Design

Astera Labs; San Jose (CA); Hybrid; USD 176,000 - 195,000; Full time

Job summary

Astera Labs is seeking a Tech Lead Engineer to drive front-end digital design for high-performance switch ASICs that enable rack-scale AI infrastructure. In CCE2, you will translate microarchitecture into robust RTL and lead block-level execution across synthesis, timing, verification, DFT, and physical implementation.

This is an opportunity to own critical connectivity technology from architecture through GDS while partnering across design, verification, physical design, and systems teams.

Qualifications

• Bachelor's degree in Electrical Engineering or related field.
• 5-8 years of experience developing or supporting complex SoC or silicon products for switch ASIC, networking, server, or storage applications.
• Hands-on experience with high-speed protocols, including UALink, UCI, PCIe Gen 6/7, ESUN, and Ethernet.
• Proven front-end digital design experience spanning architecture, RTL, simulation, synthesis, timing closure, gate-level simulation, and DFT.
• Experience owning blocks from architecture through GDS and working with Synopsys and/or Cadence design tools and flows.
• Authorized to work in the United States.

Responsibilities

• Define microarchitecture and implement synthesizable RTL for complex switch ASIC blocks.
• Develop front-end design solutions for high-performance networking and server connectivity applications.
• Integrate and configure reusable IP while ensuring clean interfaces, performance, and maintainability.
• Drive block-level execution through synthesis, timing closure, gate-level simulation, DFT, and GDS delivery.
• Analyze design tradeoffs across performance, power, area, and schedule, and resolve implementation issues with cross-functional partners.
• Apply Synopsys and/or Cadence digital design flows to deliver production-quality silicon.
• Partner with design verification engineers to define plans, debug failures, and improve coverage using UVM-based methodologies.
• Support silicon bring-up, lab debug, and root-cause analysis for complex connectivity issues.
• Provide technical leadership, prioritize multiple workstreams, and communicate risks and progress clearly to stakeholders.

Skills

Front-end RTL design

RTL design

Synthesis

Timing closure

DFT

GDS delivery

Design tools (Synopsys Cadence)

UCI/UAlink/PCIe Gen6/7/Ethernet

Education

Bachelor's degree in Electrical Engineering

Master's degree preferred

Tools

Synopsys

Cadence

GDS tooling

Job description

Astera Labs is seeking a Tech Lead Engineer to drive front-end digital design for high-performance switch ASICs that enable rack-scale AI infrastructure. In CCE2, you will translate microarchitecture into robust RTL and lead block-level execution across synthesis, timing, verification, DFT, and physical implementation.

This is an opportunity to own critical connectivity technology from architecture through GDS while partnering across design, verification, physical design, and systems teams.