Tech Lead, Verification - High-Speed AI Connectivity ASICs

Astera Labs; San Jose (CA); On-site; USD 150,000 - 210,000; Full time

Benefits offered by this job

Flexible time off

Parental leave

401K

Retirement and pension plans

Medical, dental, and vision

Job summary

Astera Labs in San Jose, CA, is seeking a Tech Lead Engineer, Design Verification to define and deliver robust verification for next‑generation connectivity silicon that enables rack‑scale AI infrastructure.

You will lead testbench architecture, coverage, checkers, and scoreboards, working with RTL, firmware, and post‑silicon teams to prove PCIe Gen 6/7, UALink and UCIe behavior in demanding data‑center environments.

Qualifications

• 5–8 years of experience in design verification for complex ASICs or SoCs.
• Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related technical field.
• Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• Experience with simulation, waveform-debug, regression, and coverage tools.
• Hands-on experience with SystemVerilog and UVM-based verification environments.

Responsibilities

• Define and deliver robust verification for next-generation connectivity silicon.
• Partner with RTL, architecture, firmware, and post-silicon teams on verification strategies.
• Lead verification planning and execution for assigned features, tracking risks and milestones.
• Build and enhance reusable UVM-based testbenches, agents, sequences, and monitors.
• Drive functional and code coverage analysis and regression strategies.
• Communicate verification status and recommendations to stakeholders.

Skills

Technical leadership

Debugging

Communication

Collaboration

Fast-paced environment

Education

Bachelor’s degree in Electrical/Computer Engineering

Master’s degree in Electrical/Computer Engineering

Tools

SystemVerilog

UVM

Python

PowerShell

Tcl

Job description

Astera Labs in San Jose, CA, is seeking a Tech Lead Engineer, Design Verification to define and deliver robust verification for next‑generation connectivity silicon that enables rack‑scale AI infrastructure.

You will lead testbench architecture, coverage, checkers, and scoreboards, working with RTL, firmware, and post‑silicon teams to prove PCIe Gen 6/7, UALink and UCIe behavior in demanding data‑center environments.