Senior Verification Engineer, AI Connectivity & PCIe

Astera Labs; San Jose, Northern (CA, KY); Hybrid; USD 149,000 - 165,000; Full time

Job summary

Astera Labs is seeking a Senior Design Verification Engineer to drive robust verification for next‑gen connectivity silicon enabling rack‑scale AI infrastructure. You will partner with RTL, architecture, firmware and post‑silicon teams to validate complex switching across PCIe Gen6/Gen7, UALink, and related protocols.

You will own testbench architecture, define coverage models, and lead regression strategies to ensure silicon readiness.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical field.
• 2–5 years of design verification experience for complex ASICs or SoCs.
• Hands-on experience with SystemVerilog and UVM-based verification environments.
• Experience developing verification plans, testbenches, assertions, scoreboards, and functional coverage models.
• Familiarity with simulation, waveform-debug, regression, and coverage tools.
• Strong debugging, communication, and collaboration skills in a fast-paced product development environment.

Responsibilities

• Define verification strategy and planning from specifications and designs.
• Build and enhance UVM-based testbenches, agents, sequences, monitors, and reference models.
• Create directed, constrained-random, and power-on-reset scenarios for PCIe Gen 6/Gen 7, UALink, and UCI behavior.
• Debug simulation failures using waveform analysis, logs, and cross-functional collaboration.
• Drive functional and code coverage analysis and close gaps to milestones.
• Develop regression strategies and automation to improve test quality and turnaround time.

Skills

SystemVerilog

UVM

Verification plans

Testbenches

Functional coverage

Debugging

Communication

Education

Bachelor's degree in Electrical/Computer Engineering

Master’s degree (preferred)

Tools

Python

Perl

Tcl

Job description

Astera Labs is seeking a Senior Design Verification Engineer to drive robust verification for next‑gen connectivity silicon enabling rack‑scale AI infrastructure. You will partner with RTL, architecture, firmware and post‑silicon teams to validate complex switching across PCIe Gen6/Gen7, UALink, and related protocols.

You will own testbench architecture, define coverage models, and lead regression strategies to ensure silicon readiness.