Senior Design Verification Engineer: PCIe/UALink for AI Infra

Asteralabs; San Jose (CA); On-site; USD 149,000 - 165,000; Full time

Job summary

Astera Labs in San Jose, CA, seeks a Senior Design Verification Engineer to define and deliver robust verification for next-generation connectivity silicon that enables rack-scale AI infrastructure. You will partner with RTL, architecture, firmware and post-silicon teams to build verification strategies proving complex switching across high-bandwidth protocols and demanding system environments.

This role spans planning, testbench architecture, coverage closure and silicon learning, contributing

Qualifications

• Bachelor’s degree in Electrical Engineering, Computer Engineering or related field.
• Hands-on verification experience with ASICs/SoCs and standard verification flows.
• Proficiency with SystemVerilog, UVM, testbenches and coverage models.

Responsibilities

• Define verification strategy and plans from specs and design requirements.
• Build reusable UVM-based testbenches, agents, sequences and monitors.
• Drive coverage analysis and regression to milestones.

Skills

SystemVerilog

UVM

Testbenches

Verification planning

Debugging

Education

Bachelor's degree in Electrical Engineering

Master's degree in Electrical/Computer Engineering

Tools

Python

Perl

Tcl

Job description

Astera Labs in San Jose, CA, seeks a Senior Design Verification Engineer to define and deliver robust verification for next-generation connectivity silicon that enables rack-scale AI infrastructure. You will partner with RTL, architecture, firmware and post-silicon teams to build verification strategies proving complex switching across high-bandwidth protocols and demanding system environments.

This role spans planning, testbench architecture, coverage closure and silicon learning, contributing