Test Architecture Lead for High-Speed AI Interfaces

Astera Labs; San Jose (CA); On-site; USD 180,000 - 250,000; Full time

Job summary

Astera Labs (NASDAQ: ALAB) is building the high-speed connectivity that powers rack-scale AI infrastructure. We're looking for a Senior Principal Test Engineer who can own test strategy and test hardware for our complex mixed-signal silicon—and move fast.

You will lead test strategies for PCIe, Ethernet, CXL, NVLink, and UALink, architect custom tester hardware, validate hardware before mass production, and mentor the team in a fast-growing environment.

Qualifications

• 12-20 years in Test or Product Engineering through high-volume manufacturing.
• Proven experience building custom test solutions for high-speed mixed-signal products.
• Strong knowledge of high-speed protocols and physical-layer behavior (PCIe, Ethernet, etc.).
• Experience designing custom Test Hardware for high-volume PCBA manufacturing.
• Bachelor's in EE or related field (Master's/PhD preferred).

Responsibilities

• Define and drive test strategies that hit quality, yield, test-time, and cost targets.
• Architect and guide design of custom Tester HW and validation boards.
• Validate and characterize test hardware before it hits mass production.
• Lead root-cause and yield improvement using deep physical-layer knowledge.
• Partner tightly with Design, DFT, Product Engineering, and Operations.
• Set technical direction and mentor the team in a high-growth environment.

Skills

Test strategy

Custom tester hardware

High-volume manufacturing

Mixed-signal testing

High-speed protocols

PCIe

Ethernet

DFT collaboration

Leadership

Mentoring

Education

Bachelor's in EE or related field

Master's or PhD preferred

Tools

Custom Tester HW design

Validation boards design

Job description

Astera Labs (NASDAQ: ALAB) is building the high-speed connectivity that powers rack-scale AI infrastructure. We're looking for a Senior Principal Test Engineer who can own test strategy and test hardware for our complex mixed-signal silicon—and move fast.

You will lead test strategies for PCIe, Ethernet, CXL, NVLink, and UALink, architect custom tester hardware, validate hardware before mass production, and mentor the team in a fast-growing environment.