Technical Lead Engineer (Design Verification)

Astera Labs; San Jose (CA); On-site; USD 150,000 - 210,000; Full time

Benefits offered by this job

Flexible time off

Parental leave

401K

Retirement and pension plans

Medical, dental, and vision

Job summary

Astera Labs in San Jose, CA, is seeking a Tech Lead Engineer, Design Verification to define and deliver robust verification for next‑generation connectivity silicon that enables rack‑scale AI infrastructure.

You will lead testbench architecture, coverage, checkers, and scoreboards, working with RTL, firmware, and post‑silicon teams to prove PCIe Gen 6/7, UALink and UCIe behavior in demanding data‑center environments.

Qualifications

• 5–8 years of experience in design verification for complex ASICs or SoCs.
• Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related technical field.
• Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• Experience with simulation, waveform-debug, regression, and coverage tools.
• Hands-on experience with SystemVerilog and UVM-based verification environments.

Responsibilities

• Define and deliver robust verification for next-generation connectivity silicon.
• Partner with RTL, architecture, firmware, and post-silicon teams on verification strategies.
• Lead verification planning and execution for assigned features, tracking risks and milestones.
• Build and enhance reusable UVM-based testbenches, agents, sequences, and monitors.
• Drive functional and code coverage analysis and regression strategies.
• Communicate verification status and recommendations to stakeholders.

Skills

Technical leadership

Debugging

Communication

Collaboration

Fast-paced environment

Education

Bachelor’s degree in Electrical/Computer Engineering

Master’s degree in Electrical/Computer Engineering

Tools

SystemVerilog

UVM

Python

PowerShell

Tcl

Job description

• As a Tech Lead Engineer, Design Verification, you will define and deliver robust verification for next-generation connectivity silicon that enables rack-scale AI infrastructure
• You will partner closely with RTL, architecture, firmware, and post-silicon teams to build verification strategies that prove complex switching behavior across high-bandwidth protocols and demanding system environments
• Within CCE2, you will lead meaningful verification challenges from planning and testbench architecture through coverage closure and silicon learning
• You will contribute to Astera Labs’ hyper-growth mission by helping deliver highly reliable PCIe and UALink connectivity products that keep AI accelerators, memory, and compute resources operating at scale
• Verification Strategy and Planning
• Develop block- and subsystem-level verification plans from specifications, architecture, and design requirements
• Define test scenarios, coverage models, checkers, assertions, and scoreboards for complex switching functionality
• Review designs and verification plans with architecture and RTL teams to identify corner cases early
• Lead verification planning and execution for assigned features, tracking risks, milestones, and quality metrics
• Environment Development and Execution
• Build and enhance reusable UVM-based SystemVerilog testbenches, agents, sequences, monitors, and reference models
• Create directed, constrained-random, and power-on-reset scenarios spanning PCIe Gen 6/Gen 7, UALink, and UCIe behavior
• Debug simulation failures using waveform analysis, logs, assertions, and cross-functional collaboration
• Partner with RTL and firmware teams to refine interfaces, improve observability, and resolve functional issues
• Coverage, Quality, and Silicon Readiness
• Drive functional and code coverage analysis, identify verification gaps, and close coverage to agreed milestones
• Develop regression strategies and automation to improve test quality, turnaround time, and failure triage
• Partner with design and post-silicon teams on issue isolation, root-cause analysis, and silicon bring-up readiness
• Communicate verification status, risks, and recommendations to technical stakeholders and project leadership

Benefits

• Flexible time off in the US
• Parental leave
• 401K
• Retirement and pension plans
• Competitive medical, dental and vision plans

Hands-on experience with SystemVerilog and UVM-based verification environments5–8 years of experience in design verification for complex ASICs or SoCsStrong technical leadership, debugging, communication, and collaboration skills in a fast-paced product development environmentBachelor’s degree in Electrical Engineering, Computer Engineering, or a related technical fieldFamiliarity with simulation, waveform-debug, regression, and coverage toolsExperience developing verification plans, testbenches, assertions, scoreboards, and functional coverage modelsMaster’s degree in Electrical Engineering, Computer Engineering, or a related fieldKnowledge of protocol checkers, formal verification, emulation, or hardware acceleration methodologiesExperience with Python, PowerShell, or Tcl for verification automation and regression infrastructureExperience verifying PCIe, UALink, UCIe, or other high-speed connectivity and switching protocolsUnderstanding of AI or data-center system architectures, including accelerator, memory, and fabric connectivity