Principal SerDes/PHY Verification Lead

Astera Labs; San Jose (CA); On-site; USD 160,000 - 200,000; Full time

Job summary

Astera Labs is hiring a Principal Design Verification Engineer to own the functional verification of our high-speed SerDes/PHY IP—the connectivity engine powering rack-scale AI infrastructure. You will architect verification environments, drive coverage closure, and ensure first-pass silicon success at the analog/digital boundary.

You will partner with PHY analog/mixed-signal designers, digital architects, and SoC integration teams to verify multi-Gbps SerDes blocks used in PCIe Gen 6/Gen 7,

Qualifications

• Expert-level proficiency in SystemVerilog and UVM.
• Hands-on analog/mixed-signal co-simulation and RNM.
• Experience with PCIe, UALink, UCIe, Ethernet, or CXL protocols.

Responsibilities

• Architect UVM-based verification environments for SerDes/PHY IP including PMA/PCS.
• Define verification plans, coverage models, and sign-off criteria for high-speed links.
• Develop SystemVerilog/UVM testbenches, sequences, scoreboards, and reference models.
• Lead coverage analysis, debug failures with designers, drive regressions to tape-out.

Skills

Verification architecture

SystemVerilog

UVM

SerDes/PHY IP

PCIe Gen6/Gen7

RNM

VLSI verification

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, or related field

MS or PhD in Electrical Engineering or Computer Engineering

Job description

Astera Labs is hiring a Principal Design Verification Engineer to own the functional verification of our high-speed SerDes/PHY IP—the connectivity engine powering rack-scale AI infrastructure. You will architect verification environments, drive coverage closure, and ensure first-pass silicon success at the analog/digital boundary.

You will partner with PHY analog/mixed-signal designers, digital architects, and SoC integration teams to verify multi-Gbps SerDes blocks used in PCIe Gen 6/Gen 7,