Senior Design Verification Engineer - High-Speed SerDes/PHY

Astera Labs; San Jose (CA); On-site; USD 207,000 - 230,000; Full time

Job summary

Astera Labs is seeking a Principal Design Verification Engineer to own the functional verification of high-speed SerDes/PHY IP that powers next-generation AI infrastructure. You will architect verification environments, drive coverage, and ensure first-pass silicon success across analog/digital boundaries while partnering with PHY analog/mixed-signal designers and SoC teams.

The role involves leading verification strategy, developing SystemVerilog/UVM testbenches, and coordinating across

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or related field
• 8+ years of design verification experience on high-speed SerDes, PHY, or mixed-signal IP
• Strong understanding of physical layer concepts: equalization, CDR, training sequences, and link bring-up
• Expert-level proficiency in SystemVerilog and UVM
• Hands-on experience with analog/mixed-signal co-simulation and RNM
• Knowledge of PCIe, UALink, UCIe, Ethernet, or CXL SerDes IP

Responsibilities

• Architect UVM-based verification environments for SerDes/PHY IP, including PMA, PCS, and PHY-MAC interface layers
• Define verification plans, coverage models, and sign-off criteria for high-speed serial link blocks
• Drive methodology decisions across analog/mixed-signal co-simulation, gate-level simulation, and emulation flows
• Develop SystemVerilog/UVM testbenches, sequences, scoreboards, and reference models for multi-Gbps SerDes lanes
• Execute functional, performance, and corner-case verification across equalization, CDR, training, and link bring-up
• Lead coverage analysis and closure, debug failures with designers, drive regressions to tape-out
• Verify PHY behavior against PCIe Gen 6/Gen 7, UALink, UCIe, Ethernet PHY standards
• Model and validate channel behavior, link training state machines, and analog handoff scenarios
• Partner with analog/AMS designers on RNM and behavioral models for SerDes blocks
• Mentor junior DV engineers and collaborate with SoC integration teams
• Contribute to verification IP reuse and tooling improvements across product lines

Skills

SystemVerilog

UVM

RNM

Analog/mixed-signal

Palladium

Education

Bachelor's in Electrical/Computer Engineering

MS/PhD in EE/CE

Tools

Palladium

Veloce

ZeBu

Python

Job description

Astera Labs is seeking a Principal Design Verification Engineer to own the functional verification of high-speed SerDes/PHY IP that powers next-generation AI infrastructure. You will architect verification environments, drive coverage, and ensure first-pass silicon success across analog/digital boundaries while partnering with PHY analog/mixed-signal designers and SoC teams.

The role involves leading verification strategy, developing SystemVerilog/UVM testbenches, and coordinating across