Principal Digital Design Engineer — High‑Speed SoC & PCIe Expert

Astera Labs; San Jose (CA); Hybrid; USD 185,000 - 240,000; Full time

Job summary

Astera Labs seeks a Principal Digital Design Engineer to lead front-end circuit design for high-performance network controllers, including RTL, synthesis, IP integration, and block-level verification.

You will bring 8+ years in SoC/silicon for Switch ASIC, Networking, Server or Storage, with strong PCIe/Ualink/Esun/Ethernet experience and familiarity with Synopsys or Cadence flows; UVM verification and DFT are valued. San Jose, CA preferred.

Qualifications

• Bachelor's degree in electrical engineering required
• 8+ years experience in SoC/silicon products for networking/server/storage
• Proactive, customer-minded with ability to work with minimal supervision

Responsibilities

• Lead front-end circuit design including RTL, synthesis, IP integration
• Drive block-level verification and GDS from architecture to production
• Own design flows and ensure testability and DFT readiness

Education

Bachelor's degree in EE

Master's degree preferred

Tools

Synopsys

Cadence

Job description

Astera Labs seeks a Principal Digital Design Engineer to lead front-end circuit design for high-performance network controllers, including RTL, synthesis, IP integration, and block-level verification.

You will bring 8+ years in SoC/silicon for Switch ASIC, Networking, Server or Storage, with strong PCIe/Ualink/Esun/Ethernet experience and familiarity with Synopsys or Cadence flows; UVM verification and DFT are valued. San Jose, CA preferred.