Tech Lead, Digital Design Engineer

Astera Labs; San Jose (CA); On-site; USD 140,000 - 230,000; Full time

Job summary

Astera Labs in San Jose, CA, seeks Senior Digital Design Engineers to advance front-end circuit design for high-performance network controllers. You will drive RTL, synthesis, IP integration, and block-level verification across PCIe, Ethernet, UALink, and related protocols.

The role requires a strong EE background with a Bachelor's, 3+ years of SoC experience, and hands-on design using Synopsys/Cadence flows. US work authorization is required.

Qualifications

• Bachelor's in EE required; Master's preferred.
• +3 years' experience with SoC/silicon products for networking/server storage.
• Strong RTL, synthesis, timing, and verification skills.
• End-to-end ownership from architecture to GDS.
• Experience with Synopsys/Cadence tool flows.
• DFT, UVM, silicon bring-up experience.
• Familiarity with PCIe, Ethernet, Ualink, Esun.

Responsibilities

• Develop front-end circuit design for high-performance network controllers.
• RTL development, synthesis, IP integration, and block-level verification.
• Lead timing closure and DFT, plus GDS flow ownership.
• Collaborate on PCIe, Ethernet, UALink, and related protocols.
• Bring-up and debug silicon; support for design verification.

Skills

RTL design

UVM verification

PCIe

Ethernet

Ualink

Esun

Scripting Python

DFT

Timing closure

GDS flow

Cadence/Synopsys tools

Silicon bring-up

Education

Bachelor's degree in EE

Master's degree preferred

Tools

Synopsys tools

Cadence tools

Job description

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.

Job Description

We are looking for Senior Digital Design Engineers with experience developing micro-architecture and implementation of the front-end circuit design, including RTL, synthesis, IP integration, and block-level verification for high performance network controllers.

The candidate must have good knowledge of communication/interface protocols such as PCI-Express (Gen-3 and above), Ualink, Esun, Ethernet etc.

Basic Qualifications

• Strong academic and technical background in electrical engineering. A Bachelor's degree in EE is required, and a Master's degree is preferred.
• +3 years’ experience supporting or developing complex SoC/silicon products for Switch ASIC, Networking applications and/or Server, Storage.
• Professional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and prepare for customer meetings in advance, and work with minimal guidance and supervision.
• Entrepreneurial, open-mind behavior and can-do attitude. Think and act fast with the customer in mind!
• Authorized to work in the US and start immediately.

Required Experience

• Hands-on, thorough knowledge of high-speed protocols like PCIe, Ualink, Esun, Ethernet, etc.
• Proven front end design skill - architecture, RTL, simulations, synthesis, timing closure, GLS, DFT etc.
• Block level ownership from architecture to GDS.
• Experience with Synopsys and/or Cadence digital design tools/flows
• Knowledge of design for test (DFT)
• Familiarity with UVM based design verification
• Silicon bring-up and debug experience
• Small-geometry CMOS (≤28nm) design

Preferred Experience

• Scripting with Python or other equivalent programming languages.
• Development/support for PCIe or Ethernet Switch products.

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.