SV/UVM Verification Engineer — SoC Power & Debug

Wipro

Santa Clara (UT)

On-site

USD 60,000 - 140,000

Full time

4 days ago
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Benefits offered by this job

Medical and dental benefits
Disability insurance
Paid time off

Job summary

Wipro is seeking a verification engineer with 3–5 years of HVL experience to design UVM/SystemVerilog environments for IP, subsystem and SoC testing. You will develop directed and random test cases, analyze coverage, and work with RTL teams to debug issues while executing regressions and driving improvements.

Ideal candidates understand SV/UVM, AMBA protocols, and power-aware simulations; you will collaborate with DFT/PD/RTL groups and document environments, plans and results for reviews.

Qualifications

  • 3–5 years of HVL verification experience.
  • Strong understanding of SV and UVM.
  • Experience with AMBA protocols.

Responsibilities

  • Build UVM/SystemVerilog verification environments for IP/subsystem/SoC testing.
  • Develop directed and random testcases and perform coverage analysis.
  • Debug simulation failures with RTL designers to resolve issues.
  • Execute regression runs and contribute to continuous improvements.
  • Integrate and run power-aware simulations using UPF/CPF as needed.
  • Collaborate with DFT/PD/RTL teams and post-silicon validation.
  • Document test environments, test plans and results.

Skills

SV/UVM
Debugging
AMBA protocols
Test plans
UVM SystemVerilog
Testbench development
Coverage analysis
Regression tests
Power-aware sim
DFT/RTL collaboration
Documentation

Tools

UPF/CPF
Verilog/SystemVerilog
VCS/Verdi

Job description

Wipro is seeking a verification engineer with 3–5 years of HVL experience to design UVM/SystemVerilog environments for IP, subsystem and SoC testing. You will develop directed and random test cases, analyze coverage, and work with RTL teams to debug issues while executing regressions and driving improvements.

Ideal candidates understand SV/UVM, AMBA protocols, and power-aware simulations; you will collaborate with DFT/PD/RTL groups and document environments, plans and results for reviews.

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