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Wipro is seeking a verification engineer with 3–5 years of HVL experience to design UVM/SystemVerilog environments for IP, subsystem and SoC testing. You will develop directed and random test cases, analyze coverage, and work with RTL teams to debug issues while executing regressions and driving improvements.
Ideal candidates understand SV/UVM, AMBA protocols, and power-aware simulations; you will collaborate with DFT/PD/RTL groups and document environments, plans and results for reviews.
Wipro is seeking a verification engineer with 3–5 years of HVL experience to design UVM/SystemVerilog environments for IP, subsystem and SoC testing. You will develop directed and random test cases, analyze coverage, and work with RTL teams to debug issues while executing regressions and driving improvements.
Ideal candidates understand SV/UVM, AMBA protocols, and power-aware simulations; you will collaborate with DFT/PD/RTL groups and document environments, plans and results for reviews.