VLSI Design Verification Engineer - UVM/AMBA

Wipro; Santa Clara (CA); On-site; USD 60,000 - 140,000; Full time

Job summary

Wipro Limited in Santa Clara is seeking an experienced verification engineer to design and implement UVM-based testbenches for IP/subsystem/SoC verification. Strong SV/UVM skills and debugging are required.

You will develop directed and random test cases, run regressions, analyze results, and work with RTL, DFT, PD, and post-silicon validation to ensure design quality. Knowledge of AMBA and power-aware simulations is a plus.

Qualifications

• 3-5 years of VLSI HVL verification experience.
• Strong understanding of SV and UVM and good debugging skills.
• Understanding of AMBA protocols.

Responsibilities

• Build UVM/SystemVerilog-based verification environments for IP/subsystem/SoC level testing.
• Develop directed and random testcases, perform coverage analysis, and close functional/code coverage.
• Debug simulation failures and work closely with RTL designers to resolve issues.
• Execute regression runs, analyze results, and contribute to continuous improvements.
• Integrate and run power-aware simulations, low power checks, and work with UPF/CPF as needed.
• Collaborate with DFT/PD/RTL teams and post-silicon validation to ensure design quality across domains.
• Document test environments, testplans, and results for internal and external reviews.

Skills

SV & UVM

Debugging

AMBA protocols

UVM/SystemVerilog

Job description

Wipro Limited in Santa Clara is seeking an experienced verification engineer to design and implement UVM-based testbenches for IP/subsystem/SoC verification. Strong SV/UVM skills and debugging are required.

You will develop directed and random test cases, run regressions, analyze results, and work with RTL, DFT, PD, and post-silicon validation to ensure design quality. Knowledge of AMBA and power-aware simulations is a plus.