Remote IP Verification Engineer - SystemVerilog/UVM

HCL Technologies Limited; California; Remote; USD 95,000 - 192,000; Full time

Benefits offered by this job

Medical benefits

Dental benefits

Vision benefits

Life insurance

401(k) retirement plan

Paid time off

Job summary

HCLTech is seeking a highly talented Design Verification Engineer - IP to advance innovation through IP verification and reusable verification environments. The role emphasizes SystemVerilog, UVM, RAL modeling, and thorough coverage closure.

The candidate will implement verification plans, directed and constrained-random tests, and collaborate with RTL and SoC teams to deliver high-quality collateral and sign-off readiness.

Qualifications

• Strong experience with SystemVerilog and UVM.
• Hands-on IP verification and verification environment development.
• Understanding of digital design fundamentals, RTL, FSMs, and verification methodologies.

Responsibilities

• Develop reusable SystemVerilog/UVM-based verification environments including testbenches, agents, monitors, drivers, scoreboards, sequences, and assertions.
• Develop and execute verification plans, test cases, and functional coverage models.
• Create directed and constrained-random test scenarios for IP/block-level verification.
• Integrate and debug UVCs/VIPs within the verification environment.
• Drive functional and code coverage closure and analyze coverage gaps.
• Verify RTL functionality of IP blocks including FSMs and control logic.
• Perform RAL-based register verification including access, prediction, mirroring and coverage.
• Debug RTL, protocol, testbench and verification environment issues.
• Perform regression analysis and support verification sign-off.
• Support low-power verification and GLS debugging as required.
• Collaborate with RTL design and SoC teams to deliver reusable verification collateral.

Skills

SystemVerilog

UVM

IP Verification

RTL

RAL modeling

Assertions

Coverage-driven verification

GLS debugging

Regression analysis

Debugging

Tools

UVCs/VIPs

Job description

HCLTech is seeking a highly talented Design Verification Engineer - IP to advance innovation through IP verification and reusable verification environments. The role emphasizes SystemVerilog, UVM, RAL modeling, and thorough coverage closure.

The candidate will implement verification plans, directed and constrained-random tests, and collaborate with RTL and SoC teams to deliver high-quality collateral and sign-off readiness.