SoC Design Verification Engineer | UVM & Power Debug

Avanciers Inc.; Austin (TX); On-site; USD 80,000 - 160,000; Full time

Benefits offered by this job

401(k)

Competitive salary

Job summary

A technology consulting firm is seeking a Design Verification Engineer to join the team for a full-time project. The role involves understanding SV and UVM, building verification environments, and collaborating with various technical teams. Candidates should have solid debugging skills and the ability to develop test plans. Compensation ranges from $80,000 to $160,000, depending on experience and skills.

Qualifications

• Must have strong understanding of SV and UVM.
• Good debugging skills needed.
• Must understand design specs and develop test plans.

Responsibilities

• Build UVM/System Verilog-based verification environments.
• Debug simulation failures with RTL designers.
• Execute regression runs and analyze results.
• Integrate and run power-aware simulations.

Skills

SV and UVM understanding

Debugging skills

Understanding of AMBA protocols

Test plan development

Build verification environments

Testcase development

Regression analysis

Power-aware simulations

Collaboration with DFT/PD/RTL teams

Documentation for reviews

Job description

A technology consulting firm is seeking a Design Verification Engineer to join the team for a full-time project. The role involves understanding SV and UVM, building verification environments, and collaborating with various technical teams. Candidates should have solid debugging skills and the ability to develop test plans. Compensation ranges from $80,000 to $160,000, depending on experience and skills.