Senior Verification Engineer: SystemVerilog/UVM for SoC

iFlow Inc.; Santa Clara (CA); On-site; USD 120,000 - 150,000; Full time

Job summary

iFlow Inc. is seeking a Design Verification Engineer based in Santa Clara, CA, for a long-term position. The successful candidate will possess 8-15 years of experience, showcasing a strong proficiency in SystemVerilog and UVM, alongside debugging skills.

Key responsibilities include developing verification environments for testing, performing coverage analysis, and collaborating with RTL designers to debug simulation failures while ensuring design quality across various domains.

Qualifications

• 8-15 years of experience in design verification.
• Strong understanding of design specifications.
• Ability to develop test plans based on requirements.

Responsibilities

• Develop verification environments for IP, subsystem, and SoC level testing.
• Perform coverage analysis and close functional/code coverage.
• Debug simulation failures in collaboration with RTL designers.

Skills

SystemVerilog

UVM

Debugging skills

Understanding of AMBA protocols

Job description

iFlow Inc. is seeking a Design Verification Engineer based in Santa Clara, CA, for a long-term position. The successful candidate will possess 8-15 years of experience, showcasing a strong proficiency in SystemVerilog and UVM, alongside debugging skills.

Key responsibilities include developing verification environments for testing, performing coverage analysis, and collaborating with RTL designers to debug simulation failures while ensuring design quality across various domains.