Staff DV Engineer: DDR6/UVM (Relocate to Duluth)

Renesas Electronics; Melbourne (FL); On-site; USD 150,000 - 190,000; Full time

Benefits offered by this job

Medical

Health savings account

Dental

Vision

Life insurance

Paid time off

Job summary

Renesas Electronics is seeking an experienced Staff Design Verification Engineer to join our team developing memory interface products for data centers, AI, and cloud computing. The role focuses on verifying DDR6 data buffers and future generations with SystemVerilog and UVM.

You will own verification environments, develop tests, and drive coverage across block and system levels, collaborating with design engineers to ensure robust verification and high-quality results.

Qualifications

• Bachelor's or Master's degree in Electrical/Computer Engineering, Computer Engineering, Computer Science, or related field.
• 8+ years of semiconductor design verification experience.
• Strong proficiency with SystemVerilog and hands-on experience using UVM.
• Experience developing and debugging UVM-based verification environments and testbenches.
• Experience with verification planning, functional verification, coverage, checkers, test development, and debugging.

Responsibilities

• Drive verification activities for complex digital designs at the block and system level.
• Develop and execute verification plans based on functional and performance specifications.
• Develop, maintain, and optimize SystemVerilog/UVM verification environments and testbenches.
• Develop verification tests, functional coverage, checkers, and other verification components.
• Take ownership of verification environments and verification execution for assigned blocks and features.
• Drive and monitor coverage to ensure verification goals are achieved.
• Work closely with design engineers to ensure designs meet requirements and are effectively verifiable.
• Analyze verification results, debug failures, and identify functional or design issues.
• Develop efficient, reusable verification environments and methodologies with a focus on quality, performance, and ease of use.
• Identify and implement improvements to verification processes, methodologies, and design behavior.
• Participate in feasibility studies and technical reviews.
• Serve as a technical resource within the team, providing guidance on complex verification problems and sharing best practices.
• Communicate verification status, risks, and results to project stakeholders.

Skills

SystemVerilog

UVM

Analytical thinking

Problem solving

Independent ownership

Education

Bachelor's or Master's in Electrical/Computer Engineering or related field

Tools

UVM-based verification environments

SystemVerilog testbenches

Job description

Renesas Electronics is seeking an experienced Staff Design Verification Engineer to join our team developing memory interface products for data centers, AI, and cloud computing. The role focuses on verifying DDR6 data buffers and future generations with SystemVerilog and UVM.

You will own verification environments, develop tests, and drive coverage across block and system levels, collaborating with design engineers to ensure robust verification and high-quality results.