Senior Staff SystemVerilog/UVM Verification Lead

Renesas Electronics; Orlando (FL); On-site; USD 120,000 - 180,000; Full time

Benefits offered by this job

Healthcare benefits

Paid time off

Job summary

Renesas Electronics is seeking a Senior Staff Design Verification Engineer to lead verification for memory interface products used in data center, AI, and cloud environments. The role emphasizes SystemVerilog/UVM expertise and technical leadership across block and system levels.

The candidate will define verification strategies, develop test plans, and drive coverage and debugging efforts. Relocation to Duluth, GA is required, with on-site work arrangements and collaboration across design teams.

Qualifications

• Bachelor's or Master's degree in Electrical or Computer Engineering.
• 10+ years of semiconductor design verification experience.
• Deep experience in SystemVerilog and UVM.

Responsibilities

• Provide technical leadership for verification at block and system level.
• Define strategies, methodologies, and coverage approaches.
• Develop and optimize SystemVerilog/UVM environments and testbenches.
• Drive functional verification, coverage closure, and debugging.
• Mentor verification engineers across projects.
• Collaborate with design teams to ensure verifiable designs.
• Communicate risks and status to leadership.

Skills

SystemVerilog

UVM

Verification leadership

Testbench development

Debugging

Memory interfaces

Education

Electrical/Computer Engineering

Tools

Verilog simulators

Job description

Renesas Electronics is seeking a Senior Staff Design Verification Engineer to lead verification for memory interface products used in data center, AI, and cloud environments. The role emphasizes SystemVerilog/UVM expertise and technical leadership across block and system levels.

The candidate will define verification strategies, develop test plans, and drive coverage and debugging efforts. Relocation to Duluth, GA is required, with on-site work arrangements and collaboration across design teams.