Senior Staff Design Verification Engineer – Coherent Interconnect

SiFive; Austin (TX); On-site; USD 150,000 - 180,000; Full time

Benefits offered by this job

Comprehensive benefits package

Eligible for variable compensation and/or equity

Paid time off

Job summary

SiFive is seeking a Senior Staff Design Verification Engineer to lead the verification of high-performance cache-coherent interconnects. In this critical role, you will develop verification strategies, identify risks early, and work collaboratively with various teams to ensure protocol correctness and subsystem integration.

Ideal candidates will have a strong background in ASIC or SoC verification, with an emphasis on SystemVerilog and cache-coherent systems. This position requires excellent communication skills and a dedication to quality in a fast-paced environment.

Qualifications

• 8+ years of experience in ASIC or SoC design verification.
• Strong understanding of cache-coherent systems and verification semantics.
• Experience with coherent interconnect protocols like CHI, ACE, or CXL.

Responsibilities

• Own verification planning for a scalable interconnect subsystem.
• Define test plans and environments for coherent traffic.
• Drive verification of subsystem behavior across interface boundaries.

Skills

SystemVerilog

Cache-coherent systems

Python scripting

Debugging

Communication skills

Education

BS or MS in Electrical Engineering, Computer Engineering, Computer Science

Job description

Job Description

SiFive is looking for a Senior Staff Design Verification Engineer to lead verification of a next‑generation cache‑coherent interconnect subsystem used in high‑performance SoCs.

In this Senior Staff individual‑contributor role you will define verification strategy, identify risks early, solve complex subsystem‑level problems, and raise the quality bar across the broader verification effort. You will collaborate across architecture, RTL, formal, and design verification teams to verify coherent data movement, protocol correctness, ordering, flow control, quality‑of‑service behavior, and subsystem integration across multiple interfaces and bridge paths.

Responsibilities

• Own verification planning and execution for a scalable cache‑coherent interconnect subsystem, from block‑level verification through subsystem integration and signoff.
• Define verification strategy, test plans, environments, and closure criteria for coherent traffic, ordering rules, backpressure, flow control, buffering behavior, QoS, and error handling.
• Develop and maintain robust verification environments, checkers, scoreboards, assertions, stimulus, and coverage models to validate complex interconnect and protocol behavior.
• Drive verification of subsystem behavior across interface boundaries, protocol adaptation layers, and bridge paths, including CHI, ACE, CXL, and related coherent interconnect flows.
• Create high‑value directed and constrained‑random scenarios that expose corner cases in coherency, concurrency, credits, arbitration, QoS, and bandwidth‑sensitive behavior.
• Partner closely with architecture, RTL, formal, and software teams to review specifications, close ambiguities early, and improve overall verification quality.
• Debug failures efficiently, isolate root cause, and drive fixes across RTL, assertions, testbench infrastructure, and test content.
• Contribute to methodology and infrastructure improvements that benefit the broader horizontal interconnect verification effort.
• Mentor engineers and help raise verification quality across the team.

Minimum Qualifications

• BS or MS in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• 8+ years of experience in ASIC or SoC design verification, with depth appropriate for a Senior Staff / T5 role.
• Strong hands‑on experience with SystemVerilog and building reusable verification infrastructure for complex hardware subsystems.
• Strong understanding of cache‑coherent systems, on‑chip interconnects, memory subsystem behavior, and verification of ordering and flow‑control semantics.
• Strong protocol knowledge in CHI, ACE, CXL, AXI, or similar coherent and high‑performance interconnect standards.
• Experience creating test plans, assertions, coverage models, and debug workflows for complex hardware subsystems.
• Strong scripting and automation skills in Python or similar languages.
• Strong communication skills and the ability to work effectively across architecture, RTL, and verification teams in a fast‑moving environment.

Preferred Qualifications

• Experience verifying coherent interconnect, cache, or memory‑subsystem IP in high‑performance SoCs.
• Experience with protocol‑conversion or bridge‑heavy subsystems.
• Experience with formal verification, performance‑oriented verification, or emulation/FPGA‑assisted debug.
• Demonstrated technical leadership and the ability to influence verification quality beyond immediate ownership.

What Success Looks Like

• Verification plans are complete, concrete, and aligned to real architectural risks.
• Critical bugs are found early, reproduced efficiently, and closed with durable fixes.
• Coverage and test quality improve meaningfully under your ownership.
• The coherent interconnect verification effort becomes more scalable, predictable, and reusable because of your contributions.
• Design and architecture teams rely on you as a strong technical partner for difficult verification and debug problems.

Additional Information

This position requires successful background and reference checks and satisfactory proof of your right to work in the United States of America. Any offer of employment for this position is also contingent on the Company verifying that you are authorized for access to export‑controlled technology under applicable export control laws or, if you are not already authorized, our ability to obtain any necessary export license(s) or other approvals.

In addition to base pay, this role may be eligible for variable / incentive compensation and/or equity. The role is also eligible for a comprehensive, competitive benefits package which may include healthcare and retirement plans, paid time off, and more.

SiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees. As an E‑Verify employer, we use this system to confirm the employment eligibility of all new hires in accordance with federal law. All applicants will be required to complete a Form I‑9, Employment Eligibility Verification, upon hire. We do not use E‑Verify to pre‑screen job candidates and will comply with all E‑Verify regulations.