Staff Design Verification Engineer – Coherent Interconnect

SiFive; Austin (TX); On-site; USD 150,000 - 190,000; Full time

Benefits offered by this job

Healthcare benefits

401(k) retirement plan

Paid time off

Job summary

SiFive is seeking a Staff Design Verification Engineer to drive verification of a next‑generation cache coherent interconnect subsystem in high‑performance SoCs. You will own complex verification spanning data movement, protocol correctness, ordering, QoS behavior, and subsystem integration.

You will partner with architecture, design, formal, and software teams to clarify requirements, accelerate debug, and sign off on verification content and coverage.

Qualifications

• 7+ years ASIC/SoC design verification
• Strong SystemVerilog and UVM experience
• Understanding of cache coherent systems
• Experience verifying protocol behavior like ordering and flow control
• Experience building reusable testbench components and coverage
• Strong debugging skills across spec, RTL and testbench
• Ability to work across architecture, design and DV teams

Responsibilities

• Own verification planning and execution for a scalable cache coherent interconnect subsystem
• Develop verification environments, checkers, scoreboards, stimulus, and coverage models
• Verify protocol adaptation across multiple interface types and bridge paths
• Drive verification of advanced interconnect behaviors (QoS, arbitration, virtual networks)
• Define directed and constrained-random test scenarios exposing corner cases
• Analyze failures, root cause, and drive fixes across RTL, assertions and test content
• Improve verification methodology and infrastructure for broader interconnect effort
• Contribute to review quality across specs and coverage closure

Skills

SystemVerilog

UVM

Verification planning

Debugging

RTL/testbench

Cache coherence

Cross-team collaboration

Education

Bachelor's or Master's degree

Tools

Python scripting

FPGA emulation

Job description

Staff Design Verification Engineer – SiFive

The Role

SiFive is looking for a Staff Design Verification Engineer to drive verification of a next‑generation cache coherent interconnect subsystem used in high‑performance SoCs. In this role, you will own complex verification problems spanning coherent data movement, protocol correctness, ordering, quality of service behavior, and subsystem integration across multiple interface types.

Responsibilities

• Own verification planning and execution for a scalable cache coherent interconnect subsystem, from block‑level verification through subsystem integration.
• Develop and maintain robust verification environments, checkers, scoreboards, stimulus, and coverage models for coherent traffic, ordering rules, backpressure, flow control, and error handling.
• Verify protocol adaptation and integration across multiple interface types and bridge paths, including conversion, buffering, deinterleaving, and related data movement behaviors.
• Drive verification of advanced interconnect behaviors such as QoS handling, arbitration policy, virtual‑network behavior, and transport‑level correctness.
• Define high‑value directed and constrained‑random test scenarios that expose corner cases in coherency, concurrency, ordering, credits, and integration.
• Partner closely with architecture, design, formal, and software teams to clarify requirements, close ambiguities early, and accelerate debug and signoff.
• Analyze failures efficiently, isolate root cause, and drive fixes across RTL, assertions, testbench infrastructure, and test content.
• Improve verification methodology, infrastructure, and productivity for the broader interconnect verification effort.
• Contribute to review quality across specs, verification plans, coverage closure, and debug strategy.

Minimum Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• 7+ years of experience in ASIC or SoC design verification.
• Strong hands‑on experience with SystemVerilog and UVM‑based verification.
• Strong understanding of cache coherent systems, on‑chip interconnects, or memory‑system verification.
• Experience verifying complex protocol behavior such as ordering, flow control, backpressure, buffering, arbitration, and error handling.
• Experience building reusable testbench components, assertions, coverage models, and debug infrastructure.
• Strong debugging skills and ability to root‑cause issues across specification, RTL, and testbench layers.
• Ability to work effectively across architecture, design, and verification teams in a fast‑moving environment.

Preferred Qualifications

• Experience with coherent interconnects, NoCs, memory fabrics, or large subsystem integration.
• Experience with one or more industry protocols such as AXI, CHI, CXL, UCIe, or similar high‑performance interface standards.
• Experience with formal verification, performance‑oriented verification, or emulation/FPGA‑assisted debug.
• Experience verifying protocol‑conversion or bridge‑heavy subsystems.
• Familiarity with Python or other scripting languages used for DV infrastructure and automation.
• Experience mentoring other engineers and raising team‑wide verification quality.

What Success Looks Like

• Verification plans are complete, concrete, and aligned to the real architectural risks.
• Critical bugs are found early, reproduced efficiently, and closed with durable fixes.
• Coverage and test quality improve meaningfully under your ownership.
• The coherent interconnect verification effort becomes more scalable, predictable, and reusable because of your contributions.
• Design and architecture teams rely on you as a strong technical partner for difficult verification and debug problems.

Benefits

In addition to base pay, this role may be eligible for variable/incentive compensation and/or equity. The role is eligible for a comprehensive, competitive benefits package which may include healthcare and retirement plans, paid time off, and more.

Additional Information

This position requires a successful background and reference checks and satisfactory proof of your right to work in the United States of America. Any offer of employment for this position is also contingent on the Company verifying that you are authorized for access to export‑controlled technology under applicable export control laws or obtaining necessary export licenses.

SiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees. As an E‑Verify employer, we use the system to confirm the employment eligibility of all new hires in accordance with federal law. All applicants will be required to complete a Form I‑9 upon hire. We do not use E‑Verify to pre‑screen job candidates and will comply with all E‑Verify regulations.