Senior Staff Design Verification Engineer – Coherent Interconnect

SiFive; Boston (MA); On-site; USD 180,000 - 230,000; Full time

Benefits offered by this job

Healthcare

Retirement plans

Paid time off

Equity

Job summary

SiFive is seeking a Senior Staff Design Verification Engineer to lead verification of a cache‑coherent interconnect subsystem within high‑performance SoCs. You will shape verification strategy, define test plans, and collaborate across architecture, RTL, formal, and software teams to ensure protocol correctness and QoS.

You will develop scalable verification environments, checkers, scoreboards, and coverage models, while mentoring engineers and improving overall verification quality in a

Qualifications

• BS or MS in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• 8+ years of ASIC/SoC design verification experience at Senior Staff level.
• Hands‑on SystemVerilog experience and reusable verification infrastructure development.
• Understanding of cache‑coherent systems, on‑chip interconnects, memory subsystem behavior, and verification of ordering/flow control semantics.
• Proven test planning, assertions, coverage models, and debug workflows for complex subsystems.
• Strong scripting skills in Python or similar languages.
• Excellent communication and cross‑functional collaboration abilities.

Responsibilities

• Own verification planning and execution for a scalable cache‑coherent interconnect subsystem from block‑level verification through integration and signoff.
• Define verification strategy, test plans, environments, and closure criteria for coherent traffic, ordering rules, and QoS.
• Develop and maintain verification environments, checkers, scoreboards, assertions, stimulus, and coverage models.
• Drive verification across interfaces and bridge paths including CHI, ACE, CXL, and related flows.
• Create directed and constrained‑random scenarios exposing corner cases in coherency and bandwidth‑sensitive behavior.
• Mentor engineers and raise verification quality across the team.
• Collaborate with architecture, RTL, formal, and software teams to resolve ambiguities and improve verification quality.

Skills

SystemVerilog

UVM

Python

Test planning

Debugging

Education

BS/MS in EE/CE/CS

Tools

Verilog

VHDL

Job description

About SiFive

SiFive is a pioneer in RISC‑V, enabling leading technology companies with high‑performance, data‑intensive solutions across AI, machine learning, automotive, data center, mobile, and consumer markets.

Job Description

Senior Staff Design Verification Engineer – leading verification of a next‑generation cache‑coherent interconnect subsystem for high‑performance SoCs.

About the Role

Senior Staff individual‑contributor focused on defining verification strategy, identifying risk early, solving complex subsystem‑level problems, and raising the quality bar across the broader verification effort. Work across architecture, RTL, formal, and design verification teams to verify coherent data movement, protocol correctness, ordering, flow control, quality‑of‑service behaviour, and subsystem integration across multiple interfaces and bridge paths.

Responsibilities

• Own verification planning and execution for a scalable cache‑coherent interconnect subsystem, from block‑level verification through subsystem integration and signoff.
• Define verification strategy, test plans, environments, and closure criteria for coherent traffic, ordering rules, backpressure, flow control, buffering behaviour, QoS, and error handling.
• Develop and maintain robust verification environments, checkers, scoreboards, assertions, stimulus, and coverage models to validate complex interconnect and protocol behaviour.
• Drive verification of subsystem behaviour across interface boundaries, protocol adaptation layers, and bridge paths, including CHI, ACE, CXL, and related coherent interconnect flows.
• Create high‑value directed and constrained‑random scenarios that expose corner cases in coherency, concurrency, credits, arbitration, QoS, and bandwidth‑sensitive behaviour.
• Partner closely with architecture, RTL, formal, and software teams to review specifications, close ambiguities early, and improve overall verification quality.
• Debug failures efficiently, isolate root cause, and drive fixes across RTL, assertions, testbench infrastructure, and test content.
• Contribute to methodology and infrastructure improvements that benefit the broader horizontal interconnect verification effort.
• Mentor engineers and raise verification quality across the team.

Minimum Qualifications

• BS or MS in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• 8+ years of experience in ASIC or SoC design verification at a Senior Staff level.
• Hands‑on experience with SystemVerilog and building reusable verification infrastructure for complex hardware subsystems.
• Understanding of cache‑coherent systems, on‑chip interconnects, memory subsystem behaviour, and verification of ordering and flow‑control semantics.
• Protocol knowledge in CHI, ACE, CXL, AXI, or similar coherent and high‑performance interconnect standards.
• Experience creating test plans, assertions, coverage models, and debug workflows for complex hardware subsystems.
• Strong scripting and automation skills in Python or similar languages.
• Strong communication skills and the ability to work effectively across architecture, RTL, and verification teams in a fast‑moving environment.

Preferred Qualifications

• Experience verifying coherent interconnect, cache, or memory‑subsystem IP in high‑performance SoCs.
• Experience with protocol‑conversion or bridge‑heavy subsystems.
• Experience with formal verification, performance‑oriented verification, or emulation/FPGA‑assisted debug.
• Demonstrated technical leadership and ability to influence verification quality beyond immediate ownership.

What Success Looks Like

• Verification plans are complete, concrete, and aligned to real architectural risks.
• Critical bugs are found early, reproduced efficiently, and closed with durable fixes.
• Coverage and test quality improve meaningfully under your ownership.
• The coherent interconnect verification effort becomes more scalable, predictable, and reusable because of your contributions.
• Design and architecture teams rely on you as a strong technical partner for difficult verification and debug problems.

Additional Information

In addition to base pay, this role may be eligible for variable/incentive compensation and/or equity. The position is eligible for a comprehensive benefits package, which may include healthcare, retirement plans, paid time off, and more.

This position requires a successful background and reference check and satisfactory proof of right to work in the United States of America. Offer of employment is contingent on verification of export‑control compliance.

SiFive is an equal‑opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees. As an E‑Verify employer, we use the system to confirm employment eligibility of new hires in accordance with federal law.