Staff Design Verification Engineer – Coherent Interconnect

SiFive, Inc.; Boston (MA); On-site; USD 120,000 - 160,000; Full time

Benefits offered by this job

Variable/incentive compensation

Comprehensive healthcare

Retirement plans

Paid time off

Job summary

SiFive, Inc. is seeking a Staff Design Verification Engineer in Boston to drive verification of next-generation cache-coherent interconnect subsystems. You will own complex verification problems and enhance the overall verification quality.

The ideal candidate has 7+ years of ASIC/SoC design verification experience, strong abilities in SystemVerilog and UVM, and a comprehensive understanding of cache-coherent systems.

Qualifications

• 7+ years of experience in ASIC or SoC design verification.
• Strong hands-on experience with SystemVerilog and UVM-based verification.
• Strong understanding of cache-coherent systems, on-chip interconnects, or memory-system verification.

Responsibilities

• Own verification planning and execution for a scalable cache-coherent interconnect subsystem.
• Develop and maintain robust verification environments and checkers.
• Drive verification of advanced interconnect behaviors such as QoS handling.

Skills

SystemVerilog

UVM-based verification

Debugging skills

Coherent systems knowledge

ASIC/SoC design verification

Education

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field

Job description

Role

SiFive is looking for a Staff Design Verification Engineer to drive verification of a next‑generation cache‑coherent interconnect subsystem used in high‑performance SoCs. In this role, you will own complex verification problems spanning coherent data movement, protocol correctness, ordering, quality‑of‑service behavior, and subsystem integration across multiple interface types. The scope aligns to the Interconnect horizontal area and the coherent interconnect subsystem, with adjacent responsibilities around protocol conversion, bridges, and integration behavior. This is a Staff individual‑contributor role. We are looking for someone who can go beyond executing assigned tests and instead define strategy, identify gaps early, solve complex verification problems, and raise the quality bar for the broader verification effort.

Responsibilities

• Own verification planning and execution for a scalable cache‑coherent interconnect subsystem, from block‑level verification through subsystem integration.
• Develop and maintain robust verification environments, checkers, scoreboards, stimulus, and coverage models for coherent traffic, ordering rules, backpressure, flow control, and error handling.
• Verify protocol adaptation and integration across multiple interface types and bridge paths, including conversion, buffering, deinterleaving, and related data‑movement behaviors.
• Drive verification of advanced interconnect behaviors such as QoS handling, arbitration policy, virtual‑network behavior, and transport‑level correctness.
• Define high‑value directed and constrained‑random test scenarios that expose corner cases in coherency, concurrency, ordering, credits, and integration.
• Partner closely with architecture, design, formal, and software teams to clarify requirements, close ambiguities early, and accelerate debug and signoff.
• Analyze failures efficiently, isolate root cause, and drive fixes across RTL, assertions, testbench infrastructure, and test content.
• Improve verification methodology, infrastructure, and productivity for the broader interconnect verification effort, not just the block immediately assigned to you.
• Contribute to review quality across specs, verification plans, coverage closure, and debug strategy.

Minimum Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• 7+ years of experience in ASIC or SoC design verification.
• Strong hands‑on experience with SystemVerilog and UVM‑based verification.
• Strong understanding of cache‑coherent systems, on‑chip interconnects, or memory‑system verification.
• Experience verifying complex protocol behavior such as ordering, flow control, backpressure, buffering, arbitration, and error handling.
• Experience building reusable testbench components, assertions, coverage models, and debug infrastructure.
• Strong debugging skills and ability to root‑cause issues across specification, RTL, and testbench layers.
• Ability to work effectively across architecture, design, and verification teams in a fast‑moving environment.

Preferred Qualifications

• Experience with coherent interconnects, NoCs, memory fabrics, or large subsystem integration.
• Experience with one or more industry protocols such as AXI, CHI, CXL, UCIe, or similar high‑performance interface standards.
• Experience with formal verification, performance‑oriented verification, or emulation/FPGA‑assisted debug.
• Experience verifying protocol‑conversion or bridge‑heavy subsystems.
• Familiarity with Python or other scripting languages used for DV infrastructure and automation.
• Experience mentoring other engineers and raising team‑wide verification quality.

What Success Looks Like

• Verification plans are complete, concrete, and aligned to real architectural risks.
• Critical bugs are found early, reproduced efficiently, and closed with durable fixes.
• Coverage and test quality improve meaningfully under your ownership.
• The coherent interconnect verification effort becomes more scalable, predictable, and reusable because of your contributions.
• Design and architecture teams rely on you as a strong technical partner for difficult verification and debug problems.

Benefits

• In addition to base pay, this role may be eligible for variable/incentive compensation and/or equity.
• A comprehensive, competitive benefits package may include healthcare and retirement plans, paid time off, and more.

Eligibility and Compliance

This position requires a successful background and reference checks and satisfactory proof of right to work in the United States of America. Any offer of employment is contingent on the company verifying access to export‑controlled technology under applicable export control laws or, if not already authorized, obtaining necessary export licenses or approvals.

Equal Employment Opportunity

SiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees. As an E‑Verify employer, we use this system to confirm the employment eligibility of all new hires in accordance with federal law. All applicants will be required to complete a Form I‑9, Employment Eligibility Verification, upon hire. We do not use E‑Verify to pre‑screen job candidates and will comply with all E‑Verify regulations.