Staff Design Verification Engineer CHI Interconnect Equity

Sifive; Boston (MA); On-site; USD 150,000 - 190,000; Full time

Job summary

SiFive is seeking a Staff Design Verification Engineer to lead verification for a next-generation cache-coherent interconnect subsystem with CHI-based architecture. You will own complex verification problems spanning coherent data movement, protocol correctness, ordering, snoop behavior, and flow control across multiple interfaces.

You will define verification strategy, build reusable environments, and collaborate with architecture, design, and software teams to raise overall quality and

Qualifications

• 7+ years of ASIC/SoC design verification experience.
• Strong SystemVerilog-based verification background.
• Deep knowledge of cache-coherent systems and CHI interconnects.
• Experience building checkers, scoreboards, assertions, coverage models.

Responsibilities

• Drive verification of CHI transactions across request, response, snoop, and data paths.
• Develop and maintain verification environments, protocol checkers, scoreboards, stimulus, and coverage models.
• Verify integration across caches, home nodes, request nodes, snoop filters, bridges, and protocol paths.
• Mentor engineers and contribute to verification methodology and test content.

Skills

SystemVerilog

UVM

Cache coherence

Debugging

Verilog

Python scripting

Education

Bachelor's or Master's in EE/CE/CS

Tools

SystemVerilog

Python

Job description

SiFive is seeking a Staff Design Verification Engineer to lead verification for a next-generation cache-coherent interconnect subsystem with CHI-based architecture. You will own complex verification problems spanning coherent data movement, protocol correctness, ordering, snoop behavior, and flow control across multiple interfaces.

You will define verification strategy, build reusable environments, and collaborate with architecture, design, and software teams to raise overall quality and