Staff CHI Interconnect Verification Engineer

SiFive; Austin (TX); Presencial; USD 140 000 - 210 000; Tempo integral

Vantagens oferecidas por esta oferta de emprego

Healthcare

Retirement plan

Resumo da oferta

SiFive is seeking a Staff Design Verification Engineer in Austin, TX to drive verification of a next-generation cache-coherent interconnect with CHI-based architecture. You will own complex verification problems across data movement, protocol correctness, ordering, and cross-block integration, influencing verification strategy and ensuring high-quality results.

The role requires deep debug skills, experience with SystemVerilog-based verification, and collaboration with architecture, design, and

Qualificações

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• 7+ years of experience in ASIC or SoC design verification.
• Strong hands-on experience with SystemVerilog-based verification.
• Strong understanding of cache-coherent systems, memory subsystems, and on-chip interconnects.
• Direct experience verifying coherent protocols, with strong preference for CHI.
• Strong understanding of protocol behavior including ordering, snooping, flow control, buffering, arbitration, and error handling.
• Experience building reusable checkers, scoreboards, assertions, coverage models, and debug infrastructure.
• Strong debugging skills and ability to root-cause issues across specification, RTL, and verification environment layers.
• Ability to work effectively across architecture, design, and verification teams in a fast-moving environment.

Responsabilidades

• Drive verification of CHI transactions across request, response, snoop, and data paths, including corner cases involving concurrency, hazards, deadlock avoidance, and ordering.
• Develop and maintain robust verification environments, protocol checkers, scoreboards, stimulus, and coverage models for coherent traffic, ordering rules, retries, backpressure, flow control, and error handling.
• Verify integration behavior across caches, home nodes, request nodes, snoop filters, bridges, and protocol-adaptation paths.
• Define high-value directed and constrained-random scenarios that expose corner cases in coherency, credits, buffering, arbitration, and system-level interactions.
• Partner closely with architecture, design, formal, and software teams to clarify requirements, close ambiguities early, and accelerate debug and signoff.
• Analyze failures efficiently, isolate root cause, and drive durable fixes across RTL, assertions, testbench infrastructure, and test content.
• Improve methodology, infrastructure, and debug productivity for the broader coherent interconnect verification effort.
• Contribute to review quality across specifications, verification plans, coverage closure, and debug strategy.
• Mentor other engineers through technical leadership, design reviews, and verification best practices.

Conhecimentos

SystemVerilog

CHI protocol

Coherent interconnect

Debugging

RTL debugging

DV methodology

Formação académica

Bachelor’s or Master’s in EE/CE/CS

Ferramentas

Python

Descrição da oferta de emprego

SiFive is seeking a Staff Design Verification Engineer in Austin, TX to drive verification of a next-generation cache-coherent interconnect with CHI-based architecture. You will own complex verification problems across data movement, protocol correctness, ordering, and cross-block integration, influencing verification strategy and ensuring high-quality results.

The role requires deep debug skills, experience with SystemVerilog-based verification, and collaboration with architecture, design, and