Staff Design Verification Engineer – Coherent Interconnect (CHI)

SiFive; Austin (TX); On-site; USD 140,000 - 210,000; Full time

Benefits offered by this job

Healthcare

Retirement plan

Job summary

SiFive is seeking a Staff Design Verification Engineer in Austin, TX to drive verification of a next-generation cache-coherent interconnect with CHI-based architecture. You will own complex verification problems across data movement, protocol correctness, ordering, and cross-block integration, influencing verification strategy and ensuring high-quality results.

The role requires deep debug skills, experience with SystemVerilog-based verification, and collaboration with architecture, design, and

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• 7+ years of experience in ASIC or SoC design verification.
• Strong hands-on experience with SystemVerilog-based verification.
• Strong understanding of cache-coherent systems, memory subsystems, and on-chip interconnects.
• Direct experience verifying coherent protocols, with strong preference for CHI.
• Strong understanding of protocol behavior including ordering, snooping, flow control, buffering, arbitration, and error handling.
• Experience building reusable checkers, scoreboards, assertions, coverage models, and debug infrastructure.
• Strong debugging skills and ability to root-cause issues across specification, RTL, and verification environment layers.
• Ability to work effectively across architecture, design, and verification teams in a fast-moving environment.

Responsibilities

• Drive verification of CHI transactions across request, response, snoop, and data paths, including corner cases involving concurrency, hazards, deadlock avoidance, and ordering.
• Develop and maintain robust verification environments, protocol checkers, scoreboards, stimulus, and coverage models for coherent traffic, ordering rules, retries, backpressure, flow control, and error handling.
• Verify integration behavior across caches, home nodes, request nodes, snoop filters, bridges, and protocol-adaptation paths.
• Define high-value directed and constrained-random scenarios that expose corner cases in coherency, credits, buffering, arbitration, and system-level interactions.
• Partner closely with architecture, design, formal, and software teams to clarify requirements, close ambiguities early, and accelerate debug and signoff.
• Analyze failures efficiently, isolate root cause, and drive durable fixes across RTL, assertions, testbench infrastructure, and test content.
• Improve methodology, infrastructure, and debug productivity for the broader coherent interconnect verification effort.
• Contribute to review quality across specifications, verification plans, coverage closure, and debug strategy.
• Mentor other engineers through technical leadership, design reviews, and verification best practices.

Skills

SystemVerilog

CHI protocol

Coherent interconnect

Debugging

RTL debugging

DV methodology

Education

Bachelor’s or Master’s in EE/CE/CS

Tools

Python

Job description

About SiFive

As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.
At SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.

About SiFive

As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.
Are you ready?
To learn more about SiFive’s phenomenal success and to see why we have won the GSA’s prestigious Most Respected Private Company Award (for the fourth time!), check out our website and Glassdoor pages.

Job Description:

The Role

SiFive is looking for a Staff Design Verification Engineer to drive verification of a next-generation cache-coherent interconnect subsystem with a strong focus on CHI-based architecture and protocol behavior.
In this role, you will own complex verification problems spanning coherent data movement, protocol correctness, ordering, snoop and home-node interactions, credit- and flow-control behavior, and subsystem integration across multiple interface boundaries. This is a horizontal role with broad impact across the coherent interconnect space, requiring strong technical judgment, deep debug ability, and the ability to influence verification strategy beyond an individually assigned block.
This is a Staff Engineer individual-contributor role. We are looking for someone who can define verification strategy, identify architectural and verification gaps early, solve difficult protocol and integration problems, and raise the overall quality bar for the broader interconnect verification effort.

Responsibilities

• Drive verification of CHI transactions across request, response, snoop, and data paths, including corner cases involving concurrency, hazards, deadlock avoidance, and ordering
• Develop and maintain robust verification environments, protocol checkers, scoreboards, stimulus, and coverage models for coherent traffic, ordering rules, retries, backpressure, flow control, and error handling
• Verify integration behavior across caches, home nodes, request nodes, snoop filters, bridges, and protocol-adaptation paths
• Define high-value directed and constrained-random scenarios that expose corner cases in coherency, credits, buffering, arbitration, and system-level interactions
• Partner closely with architecture, design, formal, and software teams to clarify requirements, close ambiguities early, and accelerate debug and signoff
• Analyze failures efficiently, isolate root cause, and drive durable fixes across RTL, assertions, testbench infrastructure, and test content
• Improve methodology, infrastructure, and debug productivity for the broader coherent interconnect verification effort
• Contribute to review quality across specifications, verification plans, coverage closure, and debug strategy
• Mentor other engineers through technical leadership, design reviews, and verification best practices

Minimum Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field
• 7+ years of experience in ASIC or SoC design verification
• Strong hands-on experience with SystemVerilog-based verification
• Strong understanding of cache-coherent systems, memory subsystems, and on-chip interconnects
• Direct experience verifying coherent protocols, with strong preference for CHI
• Strong understanding of protocol behavior including ordering, snooping, flow control, buffering, arbitration, and error handling
• Experience building reusable checkers, scoreboards, assertions, coverage models, and debug infrastructure
• Strong debugging skills and ability to root-cause issues across specification, RTL, and verification environment layers
• Ability to work effectively across architecture, design, and verification teams in a fast-moving environment

Preferred Qualifications

• Experience with ARM CHI or similar high-performance coherent interconnect protocols
• Experience verifying large subsystem integration involving coherent caches, bridges, or protocol-conversion paths
• Experience with memory consistency, cache coherency, and weak-ordering verification challenges
• Experience with formal verification, performance-oriented verification, or emulation-assisted debug
• Familiarity with Python or other scripting languages used for DV infrastructure and automation
• Experience mentoring engineers and driving team-wide improvements in verification quality

What Success Looks Like

• Verification plans are complete, concrete, and aligned to the real architectural and protocol risks
• Critical CHI and coherent-interconnect bugs are found early, reproduced efficiently, and closed with durable fixes
• Coverage and test quality improve meaningfully under your ownership
• The coherent interconnect verification effort becomes more scalable, predictable, and reusable because of your contributions
• Design and architecture teams rely on you as a strong technical partner for difficult protocol, coherency, and integration problems

You will be part of a high performance Out-of-Order Core team that focuses on verification of components such as Frontend, Mid-Core, Load-Store Unit, Integer and Floating Execution Unit, as well as Vector Unit that implement the latest RVV.
BS/MS Degree in EE, CE or CS
5-8 years relevant experience with IP/Component functional verification, preferably in Core/CPU verification
Deep understand of computer architecture is desired
Experienced developer using Object Oriented Programing principles
In addition to base pay, this role may be eligible for variable/ incentive compensation and/ or equity. In addition, this role is eligible for a comprehensive, competitive benefits package which may include healthcare and retirement plans, paid time off, and more!

Additional Information:

This position requires a successful background and reference checks and satisfactory proof of your right to work in
United States of America
Any offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.
SiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.
As an E-Verify employer, we use this system to confirm the employment eligibility of all new hires in accordance with federal law. All applicants will be required to complete a Form I-9, Employment Eligibility Verification, upon hire. We do not use E-Verify to pre-screen job candidates and will comply with all E-Verify regulations.