Staff Verification Engineer - CHI Interconnect

SiFive, Inc.; Boston (MA); On-site; USD 150,000 - 220,000; Full time

Benefits offered by this job

Healthcare

Equity

PTO

Job summary

SiFive is seeking a Staff Design Verification Engineer in Boston to drive verification of a next-generation cache-coherent interconnect with CHI-based architecture. You will define verification strategy, build robust environments, and collaborate across architecture, design and software teams to close gaps early.

The role requires 7+ years in ASIC/SoC verification, strong SystemVerilog skills, and deep knowledge of cache-coherent systems.

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• 7+ years of experience in ASIC or SoC design verification.
• Strong hands-on SystemVerilog-based verification experience.
• Strong understanding of cache-coherent systems, memory subsystems, and on-chip interconnects.
• Direct experience verifying coherent protocols, with strong preference for CHI.

Responsibilities

• Drive verification of CHI transactions across request, response, snoop, and data paths, including corner cases involving concurrency, hazards, deadlock avoidance, and ordering.
• Develop and maintain robust verification environments, protocol checkers, scoreboards, stimulus, and coverage models for coherent traffic, ordering rules, retries, backpressure, flow control, and error handling.
• Verify integration behavior across caches, home nodes, request nodes, snoop filters, bridges, and protocol-adaptation paths.
• Define high-value directed and constrained-random scenarios that expose corner cases in coherency, credits, buffering, arbitration, and system-level interactions.
• Partner with architecture, design, formal, and software teams to clarify requirements, close ambiguities early, and accelerate debug and signoff.
• Analyze failures efficiently, isolate root cause, and drive durable fixes across RTL, assertions, testbench infrastructure, and test content.
• Improve methodology, infrastructure, and debug productivity for the broader coherent interconnect verification effort.
• Contribute to review quality across specifications, verification plans, coverage closure, and debug strategy.
• Mentor other engineers through technical leadership, design reviews, and verification best practices

Skills

SystemVerilog verification

CHI protocol

Cache-coherence

Debugging skills

Testbench development

Mentoring engineers

Education

BS in EE/CE/CS

MS in EE/CE/CS

Tools

Python scripting

UVM

Job description

SiFive is seeking a Staff Design Verification Engineer in Boston to drive verification of a next-generation cache-coherent interconnect with CHI-based architecture. You will define verification strategy, build robust environments, and collaborate across architecture, design and software teams to close gaps early.

The role requires 7+ years in ASIC/SoC verification, strong SystemVerilog skills, and deep knowledge of cache-coherent systems.