Staff Applications Engineer: Physical Design & Automation

Synopsys Inc; San Diego (CA); On-site; USD 150,000 - 210,000; Full time

Job summary

Synopsys Inc is seeking an experienced ASIC physical design engineer to drive timing closure and implementation for 7nm and beyond. You will write scalable TCL and Python scripts, balance PPA against schedules, and guide customers through complex design tradeoffs.

You will collaborate with R&D and field teams to translate customer challenges into actionable product requirements, travel to sites when needed, and contribute to AI-driven optimization efforts that enhance RTL-to-GDS flows.

Qualifications

• Bachelor’s degree in Electrical Engineering or a related field.
• 3+ years of hands-on ASIC physical design experience with advanced-node designs.
• Proficiency with TCL, Python, or Perl for flows and automation.
• Experience with timing closure and FinFET/multi-patterning constraints.
• Ability to communicate complex design tradeoffs to engineers and management.

Responsibilities

• Support customer engagements on advanced-node designs at 7nm and below using Fusion Compiler and ICC2.
• Develop physical design methodologies and automation for RTL-to-GDS flow using TCL, Python, and Perl.
• Debug placement, clock tree synthesis, routing, timing closure, and power optimization on FinFET designs.
• Provide methodology recommendations tailored to customer constraints and project timelines.
• Contribute to AI-driven optimization initiatives and data-driven design improvements.
• Collaborate with R&D, product management, and field teams to translate customer pain points into product requirements.
• Travel to customer sites for onsite support, training, and design reviews as needed.

Skills

ASIC physical design

Scripting (TCL/Python/Perl)

Timing closure

Technical communication

On-site travel readiness

Education

B.S. in Electrical Engineering

M.S. in related field

Tools

Synopsys ICC2

Fusion Compiler

Cadence Innovus

Job description

Synopsys Inc is seeking an experienced ASIC physical design engineer to drive timing closure and implementation for 7nm and beyond. You will write scalable TCL and Python scripts, balance PPA against schedules, and guide customers through complex design tradeoffs.

You will collaborate with R&D and field teams to translate customer challenges into actionable product requirements, travel to sites when needed, and contribute to AI-driven optimization efforts that enhance RTL-to-GDS flows.