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Synopsys, Inc. seeks a seasoned ASIC physical design engineer to partner with customers on 7nm and below designs. You will build flows in TCL/Python, debug timing, routing and power challenges, and push automation that improves design quality and predictability across RTL-to-GDS workflows.
The role requires hands-on experience with Fusion Compiler, ICC2, and Cadence Innovus, plus strong scripting. Willingness to travel for onsite reviews is expected.
Synopsys, Inc. seeks a seasoned ASIC physical design engineer to partner with customers on 7nm and below designs. You will build flows in TCL/Python, debug timing, routing and power challenges, and push automation that improves design quality and predictability across RTL-to-GDS workflows.
The role requires hands-on experience with Fusion Compiler, ICC2, and Cadence Innovus, plus strong scripting. Willingness to travel for onsite reviews is expected.