Senior Staff Physical Design Engineer: AI-Driven Signoff

Synopsys, Inc.; Sunnyvale (CA); On-site; USD 180,000 - 280,000; Full time

Job summary

Synopsys, Inc. seeks an experienced ASIC physical design engineer to drive timing closure for advanced-node designs and lead signoff readiness across block, subsystem, and full-chip implementations.

You will build repeatable design flows using TCL, Python, and Perl, and work with PrimeTime, ICC2, Fusion Compiler, and Cadence tools, collaborating with CAD, verification, and frontend teams to ship silicon on schedule.

Qualifications

• 8+ years of hands-on ASIC physical design and timing closure experience.
• Proven ability to develop and optimize design flows and signoff readiness.
• Experience with advanced-node designs (7nm+).
• Strong scripting skills in TCL, Python, or Perl.

Responsibilities

• Drive timing closure and signoff readiness for advanced-node designs across block, subsystem, and full-chip implementations.
• Develop and refine physical design methodologies and automation flows to improve quality and predictability.
• Perform static timing analysis and ECO implementation using PrimeTime, ICC2, Fusion Compiler.
• Collaborate with front-end design, verification, and CAD teams to ensure timely silicon delivery.
• Contribute to AI-assisted design optimization initiatives and scalable technical solutions.

Skills

ASIC physical design

Timing closure

Automation scripting

Cross-functional collaboration

Global team collaboration

Education

Bachelor's or Master's in Electrical/Computer Engineering

Tools

Synopsys ICC2

Fusion Compiler

Cadence Innovus

PrimeTime

PrimeTime PX

Job description

Synopsys, Inc. seeks an experienced ASIC physical design engineer to drive timing closure for advanced-node designs and lead signoff readiness across block, subsystem, and full-chip implementations.

You will build repeatable design flows using TCL, Python, and Perl, and work with PrimeTime, ICC2, Fusion Compiler, and Cadence tools, collaborating with CAD, verification, and frontend teams to ship silicon on schedule.