Senior ASIC Physical Design & Tool Optimization Engineer

Synopsys, Inc.

Sunnyvale (CA)

On-site

USD 180,000 - 240,000

Full time

14 days+

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Job summary

Synopsys, Inc. is seeking an experienced ASIC physical design engineer to drive complex flows from RTL to GDS. You will work directly with customers, translate constraints into concrete plans using Fusion Compiler or ICC2, and push for timely tapeouts at advanced nodes.

The role emphasizes hands‑on tool usage, method development, and clear technical communication to management and engineering teams. Your work will focus on supporting customer engagements, debugging challenging issues, and

Qualifications

Bachelor's or higher in Electrical Engineering or equivalent with multi‑year ASIC design experience.
Strong background in RTL‑to‑GDS flows, placement, CTS, routing, and timing closure.
Hands‑on use of Fusion Compiler or ICC2 with advanced node optimization knowledge.

Responsibilities

Support customer engagements on Synopsys physical design tools to hit PPA targets.
Debug RTL‑to‑GDS flow issues including timing, placement, routing and CTS.
Develop methodology recommendations based on customer constraints and schedules.
Run benchmarks and proof‑of‑concepts to showcase tool capabilities and AI features.
Present technical content to customers and collaborate with cross‑functional teams.