Senior Applications Engineer, Fusion CTS & Physical Design

Synopsys, Inc.; Sunnyvale (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

Synopsys, Inc. seeks an experienced ASIC physical design engineer based in Sunnyvale, CA. You will tackle RTL-to-GDSII flows, mentor teams, and lead timing closure on advanced nodes while engaging directly with customers and ensuring successful tape-outs.

The role requires deep tool proficiency, collaboration with product teams, and travel up to 30% to customer sites, with a focus on delivering measurable PPA improvements.

Qualifications

• 9+ years hands-on ASIC physical design experience.

Responsibilities

• Support pre-sales and post-sales engagements demonstrating Synopsys physical design tools including Fusion Compiler and ICC2 in live technical sessions.

Skills

RTL-to-GDSII flows

Fusion Compiler

ICC2

Timing closure

Clock tree synthesis

Multi-scenario optimization

Noise analysis

Education

Bachelor's degree in Electrical Engineering or equivalent

Master's degree

Tools

Design Compiler

PrimeTime

Job description

Synopsys, Inc. seeks an experienced ASIC physical design engineer based in Sunnyvale, CA. You will tackle RTL-to-GDSII flows, mentor teams, and lead timing closure on advanced nodes while engaging directly with customers and ensuring successful tape-outs.

The role requires deep tool proficiency, collaboration with product teams, and travel up to 30% to customer sites, with a focus on delivering measurable PPA improvements.