Staff Physical Design Engineer: AI-Driven Timing & Automation

Synopsys, Inc.; Sunnyvale (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

Synopsys, Inc. is seeking an experienced ASIC physical design engineer in Sunnyvale, CA.

You will drive timing closure, signoff readiness, and PPA optimization for advanced-node customer designs across block, subsystem, and chip levels. You will develop methodologies and automation using TCL, Python, or Pandas, perform static timing analysis with PrimeTime and ICC2, and collaborate with cross-functional teams to deliver silicon on time.

Qualifications

• 5+ years in ASIC physical design and timing closure.
• Strong knowledge of STA, clock-tree synthesis, and ECO flows.
• Proficient scripting in TCL or Python to automate flows.

Responsibilities

• Drive timing closure and signoff for advanced-node designs.
• Develop and automate physical design methodologies and flows.
• Analyze timing data to identify bottlenecks and optimize PPA.
• Collaborate with design, verification, and CAD teams for silicon delivery.
• Contribute to AI-assisted design optimization initiatives.

Skills

ASIC Physical Design

Timing Closure

Scripting (TCL/Python)

STA/CT-Signoff

Team Collaboration

Education

Bachelor's or Master's in Electrical/Computer Engineering

Tools

ICC2

Fusion Compiler

Cadence Innovus

Job description

Synopsys, Inc. is seeking an experienced ASIC physical design engineer in Sunnyvale, CA.

You will drive timing closure, signoff readiness, and PPA optimization for advanced-node customer designs across block, subsystem, and chip levels. You will develop methodologies and automation using TCL, Python, or Pandas, perform static timing analysis with PrimeTime and ICC2, and collaborate with cross-functional teams to deliver silicon on time.