Senior SoC Physical Design Engineer - On-Site

Arrow Electronics; San Jose (CA); Sur place; USD 180 000 - 240 000; Plein temps

Avantages offerts par ce poste

Medical, Dental, Vision Insurance

401k with matching

Disability Insurance

HSA/HRA options

Paid Time Off

Résumé du poste

Arrow Electronics seeks a Physcial Design Engineer to drive ASIC implementation across partitions, executing synthesis, PNR and STA to meet tight schedules. You will collaborate with architects, RTL teams and DFT engineers to resolve signoff issues and ensure power integrity and timing closure.

The role requires 7+ years in physical design, SoC experience, and TCL scripting to automate flows.

Qualifications

• Bachelor’s degree in electrical engineering, Computer Engineering, Computer Science, or a related technical field, or equivalent practical experience.
• 7+ years of hands-on experience in physical design and implementation, including synthesis, PnR, timing convergence and physical verification.

Responsabilités

• Execute synthesis, PNR, and STA for assigned partitions of ASIC chip adhering to strict schedules and design goals.
• Work closely with architects, RTL designers, and DFT engineers to resolve implementation and signoff issues across your blocks.
• Help close EM/IR, drive LEC and physical verification signoff for your partitions in coordination with methodology owners.
• Partner with the design team to proactively identify and address potential physical design challenges, enabling efficient iteration and convergence.
• Contribute to the refinement of other implementation and physical design methodologies, encompassing synthesis, place and route (PnR), EMIR, PDN, and LEC.
• Troubleshoot flow issues and collaborate with EDA vendors to resolve them as needed.

Connaissances

Scripting TCL

Physical design

Formation

Bachelor’s degree in electrical engineering or related field

Outils

Innovus

Tempus

Quantus

Description du poste

Arrow Electronics seeks a Physcial Design Engineer to drive ASIC implementation across partitions, executing synthesis, PNR and STA to meet tight schedules. You will collaborate with architects, RTL teams and DFT engineers to resolve signoff issues and ensure power integrity and timing closure.

The role requires 7+ years in physical design, SoC experience, and TCL scripting to automate flows.