Staff Analog Designer - Timing & PLL Expert

intellipro

Santa Clara (CA)

On-site

USD 150,000 - 250,000

Full time

12 days ago
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Job summary

Intellipro is seeking an Analog Designer – Timing to join the timing product development team. This is a full-time, on-site role addressing high-speed, high-performance timing products for leading customers.

You will develop with a talented team and contribute to the product throughout its lifecycle. Responsibilities include designing modules, verifying in lab, guiding layout engineers, and participating in definition to release.

Qualifications

  • Passion for mixed-signal design with emphasis on PLL and timing products.
  • Familiar with mixed-signal IC design, methodology, and process.
  • Understanding of phase noise, jitter, and high-speed transistor modeling.
  • Knowledge of silicon physics, processes, and IC packaging technologies.
  • Awareness of thermal, mechanical, and packaging challenges; production variance.

Responsibilities

  • Contribute to timing product for high-performance networking and data center products.
  • Follow full product development process from definition to release.
  • Design key modules and integrate top-level schematics.
  • Participate in product definition, process selection, lab verification, and release to production.
  • Guide layout engineers.
  • Grow with the team and company in technical, managerial, and financial aspects.

Skills

Mixed-signal design
PLL design
Verilog-AMS modeling
High-speed I/O
Noise theory
CMOS process knowledge
Packaging & manufacturing

Education

MSEE (3+ years experience)

Tools

Cadence Spectre
AMS
Verilog-AMS

Job description

Intellipro is seeking an Analog Designer – Timing to join the timing product development team. This is a full-time, on-site role addressing high-speed, high-performance timing products for leading customers.

You will develop with a talented team and contribute to the product throughout its lifecycle. Responsibilities include designing modules, verifying in lab, guiding layout engineers, and participating in definition to release.

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