Analog Designer - Timing

Ipro Networks Pte. Ltd.; Tempe (AZ); On-site; USD 150,000 - 250,000; Full time

Job summary

Intellipro in Tempe, AZ is seeking an Analog Designer – Timing to join the timing product development team for high-performance networking and data center applications. This full-time, on-site role offers the chance to work on novel timing products with a talented team.

You will design mixed-signal modules, contribute from definition to release, and mentor layout engineers. A MSEE with 3+ years and hands-on Cadence Spectre/AMS experience are required; knowledge of PLL, phase noise, and 65nm CMOS

Qualifications

• Passion for and knowledge of mixed-signal design, especially PLL and other timing product design.
• Familiar with mixed-signal IC design, methodology, and process.
• Understand high-speed transistor modeling and circuit noise theory; solid understanding of phase noise and jitter.
• Deep knowledge of silicon physics, silicon processes, and IC packaging technologies.

Responsibilities

• Provide important contributions to the timing product for high-performance networking, communication, and data center products.
• Follow the whole product development process from product definition to release.
• Design key modules and integrate top-level schematics.
• Participate in product definition, process selection, lab verification, and release to production.
• Guide layout engineers.
• Grow with the team and company in technical, managerial, and financial aspects.

Skills

Mixed-signal design

PLL design

High-speed I/O

Verilog-AMS

Education

MSEE

Tools

Cadence Spectre

AMS

Job description

About the Role

Intellipro is hiring an Analog Designer – Timing to join the timing product development team. This is a full-time, on-site role. You will work on novel timing products addressing high-speed, high-performance requirements from the world's top customers, developing best-in-class timing products with a talented and experienced team.

Responsibilities

• Provide important contributions to the timing product for high-performance networking, communication, and data center products.
• Follow the whole product development process from product definition to release.
• Design key modules and integrate top-level schematics.
• Participate in product definition, process selection, lab verification, and release to production.
• Guide layout engineers.
• Grow with the team and company in technical, managerial, and financial aspects.

Requirements

• Passion for and knowledge of mixed-signal design, especially PLL and other timing product design.
• Familiar with mixed-signal IC design, methodology, and process.
• Understand high-speed transistor modeling and circuit noise theory; solid understanding of phase noise and jitter.
• Deep knowledge of silicon physics, silicon processes, and IC packaging technologies.
• Good understanding of thermal, mechanical, and packaging challenges; knowledge of high-volume manufacturing technologies and production variance.
• Experience with mixed-signal design tools such as Cadence Spectre and AMS.
• Able to model both modules and top level with Verilog-AMS and/or other languages.
• Experience with high-speed I/O and ESD is a plus.
• Experience with ≤65nm CMOS technologies is a plus.
• Experience with delta-sigma modulator theory is a plus.
• Education: MSEE with 3+ years of experience. Level: Staff and above.

Compensation

Base salary: USD 150,000–250,000 per year.