Analog Designer - Timing

intellipro; Santa Clara (CA); In loco; USD 150.000 - 250.000; Tempo pieno

Descrizione del lavoro

Intellipro is seeking an Analog Designer – Timing to join the timing product development team. This is a full-time, on-site role addressing high-speed, high-performance timing products for leading customers.

You will develop with a talented team and contribute to the product throughout its lifecycle. Responsibilities include designing modules, verifying in lab, guiding layout engineers, and participating in definition to release.

Competenze

• Passion for mixed-signal design with emphasis on PLL and timing products.
• Familiar with mixed-signal IC design, methodology, and process.
• Understanding of phase noise, jitter, and high-speed transistor modeling.
• Knowledge of silicon physics, processes, and IC packaging technologies.
• Awareness of thermal, mechanical, and packaging challenges; production variance.

Mansioni

• Contribute to timing product for high-performance networking and data center products.
• Follow full product development process from definition to release.
• Design key modules and integrate top-level schematics.
• Participate in product definition, process selection, lab verification, and release to production.
• Guide layout engineers.
• Grow with the team and company in technical, managerial, and financial aspects.

Conoscenze

Mixed-signal design

PLL design

Verilog-AMS modeling

High-speed I/O

Noise theory

CMOS process knowledge

Packaging & manufacturing

Formazione

MSEE (3+ years experience)

Strumenti

Cadence Spectre

AMS

Verilog-AMS

Descrizione del lavoro

About the Role

Intellipro is hiring an Analog Designer – Timing to join the timing product development team. This is a full-time, on-site role. You will work on novel timing products addressing high-speed, high-performance requirements from the world's top customers, developing best-in-class timing products with a talented and experienced team.

Responsibilities

• Provide important contributions to the timing product for high-performance networking, communication, and data center products.
• Follow the whole product development process from product definition to release.
• Design key modules and integrate top-level schematics.
• Participate in product definition, process selection, lab verification, and release to production.
• Guide layout engineers.
• Grow with the team and company in technical, managerial, and financial aspects.

Requirements

• Passion for and knowledge of mixed-signal design, especially PLL and other timing product design.
• Familiar with mixed-signal IC design, methodology, and process.
• Understand high-speed transistor modeling and circuit noise theory; solid understanding of phase noise and jitter.
• Deep knowledge of silicon physics, silicon processes, and IC packaging technologies.
• Good understanding of thermal, mechanical, and packaging challenges; knowledge of high-volume manufacturing technologies and production variance.
• Experience with mixed-signal design tools such as Cadence Spectre and AMS.
• Able to model both modules and top level with Verilog-AMS and/or other languages.
• Experience with high-speed I/O and ESD is a plus.
• Experience with 65nm or smaller CMOS technologies is a plus.
• Experience with delta-sigma modulator theory is a plus.
• Education: MSEE with 3+ years of experience. Level: Staff and above.

Compensation

Base salary: USD 150,000–250,000 per year.