Senior Analog Timing Designer – High-Performance ICs

Ipro Networks Pte. Ltd.; Tempe (AZ); Sur place; USD 150 000 - 250 000; Plein temps

Résumé du poste

Intellipro in Tempe, AZ is seeking an Analog Designer – Timing to join the timing product development team for high-performance networking and data center applications. This full-time, on-site role offers the chance to work on novel timing products with a talented team.

You will design mixed-signal modules, contribute from definition to release, and mentor layout engineers. A MSEE with 3+ years and hands-on Cadence Spectre/AMS experience are required; knowledge of PLL, phase noise, and 65nm CMOS

Qualifications

• Passion for and knowledge of mixed-signal design, especially PLL and other timing product design.
• Familiar with mixed-signal IC design, methodology, and process.
• Understand high-speed transistor modeling and circuit noise theory; solid understanding of phase noise and jitter.
• Deep knowledge of silicon physics, silicon processes, and IC packaging technologies.

Responsabilités

• Provide important contributions to the timing product for high-performance networking, communication, and data center products.
• Follow the whole product development process from product definition to release.
• Design key modules and integrate top-level schematics.
• Participate in product definition, process selection, lab verification, and release to production.
• Guide layout engineers.
• Grow with the team and company in technical, managerial, and financial aspects.

Connaissances

Mixed-signal design

PLL design

High-speed I/O

Verilog-AMS

Formation

MSEE

Outils

Cadence Spectre

AMS

Description du poste

Intellipro in Tempe, AZ is seeking an Analog Designer – Timing to join the timing product development team for high-performance networking and data center applications. This full-time, on-site role offers the chance to work on novel timing products with a talented team.

You will design mixed-signal modules, contribute from definition to release, and mentor layout engineers. A MSEE with 3+ years and hands-on Cadence Spectre/AMS experience are required; knowledge of PLL, phase noise, and 65nm CMOS