Principal PLL Design Engineer

Celero Communications, Inc.; San Jose (CA); On-site; USD 150,000 - 250,000; Full time

Job summary

Celero Communications, Inc. seeks a Principal PLL Design Engineer to lead high-speed clocking circuit development for next-generation optical transceivers and SerDes. You will architect and implement PLLs, analyze phase noise, and guide tape-out efforts.

You should have a Master’s or PhD in EE with 5+ years in PLL design, experience with 16nm–2nm nodes, Cadence Virtuoso, EMX/HFSS, and MATLAB. Excellent communication is essential, with a track record of production-level designs.

Qualifications

• Master’s degree or PhD in Electrical Engineering with 5+ years of PLL design experience.
• Experience with advanced node processes (16nm–2nm).
• Strong communication and documentation skills.

Responsibilities

• Evaluate PLL topologies (integer-N, fractional-N, ADPLL) to meet specs.
• Design and simulate analog/mixed-signal PLL blocks (VCOs, charge pumps, dividers, PFDs, loop filters) at transistor level.
• Address reliability issues in advanced nodes (self-heating, electromigration, VCO linearization).
• Review layouts to ensure floorplanning, matching, and parasitic minimization.
• Lead PLL bring-up and characterize performance in the lab.
• Perform system-level simulations for PLL integration into transceivers.

Skills

PLL design

Phase noise analysis

VCO design

LDOs

Communication skills

Education

Master's or PhD in Electrical Engineering

Tools

Cadence Virtuoso

EMX/HFSS

MATLAB

Job description

Principal PLL Design Engineer

Are you a PLL Design Engineer, who is seeking an amazing opportunity delivering disruptive High Speed Interconnect Technology to power next generation AI? We are looking for a High-Speed CMOS PLL Analog Design Engineer –who is excited to join a fast-growing Start-Up Company with a key role for expert in clocking circuits for next generation optical transceivers, high-speed SerDes, and ADC/DAC systems. Candidate will have the opportunity to architect and design PLLs for next generation transceivers.

What You Will Do

• Understand trade-offs between different PLL topologies (e.g., integer-N, fractional-N, all-digital/ADPLL) to meet specifications for power, area, jitter, and frequency range
• Architect, design and simulate analog/mixed-signal PLL building blocks (VCOs, charge pumps, dividers, PFDs, Loop Filters) at transistor level using tools like Cadence Virtuoso and Spectre
• Address challenges in advanced node technologies, such as self-heating, electromigration, voltage-controlled oscillator (VCO) linearization and device-level noise optimization
• Supervise and verify layouts produced by layout engineers to ensure floorplanning, matching, and parasitic minimization using advanced node technologies
• Be responsible for PLL bring up in the lab, conducting performance characterization using state-of-the-art lab equipment
• Conduct comprehensive system-level simulations and validation for PLL integration into advanced transceiver technologies

What You Will Bring

• Master’s degree and/or PhD in Electrical Engineering or related fields with 5+ years of relevant experience in PLL design, and production level tape-out experience.
• Must have extensive experience with advanced node technologies (16nm/12nm, 7nm, 5nm, 3nm, 2nm processes)
• Deep understanding of phase noise analysis, VCO design, LDOs and supporting circuitry associated with PLLs
• Proficient in cadence virtuoso, electromagnetic simulator (e.g., EMX/HFSS), and MATLAB for system-level modelling
• Strong communication and documentation skills

Annual Base Salary Range: $150,000 - $250,000 (The final offer will be determined based on job-related skills, experience, qualifications, and location.)