Senior Analog Design Engineer - Clocking & SerDes Lead

d-Matrix; Santa Clara (CA); On-site; USD 140,000 - 210,000; Full time

Job summary

d-Matrix is seeking a hands-on senior analog/mixed-signal designer to own the clocking subsystem of our high-speed SerDes on the IO chiplet. You will carry designs from specification through silicon characterization, porting clocking blocks to new nodes and collaborating with datapath, DSP, digital, and firmware teams to meet timing, jitter budgets, and calibration.

The role involves owning PLL/LC or ring PLL designs, phase interpolator/rotation, high-frequency clock distribution, CDR loop

Qualifications

• BS/MS/PhD in Electrical Engineering with 5+ years hands-on analog/mixed-signal design.
• Proven ownership of a low-jitter PLL, phase interpolator, or CDR loop through silicon in a high-speed SerDes.
• Deep knowledge of PLL architecture, loop dynamics, VCO design, and phase noise theory.
• Experience with jitter budgeting and decomposition in simulation.
• Circuit design in advanced FinFET or GAA nodes with Cadence tools and standard analog methodologies.
• Silicon bring-up and bench debugging with phase noise analyzers, high-speed scopes, and BERTs.

Responsibilities

• Own transistor-level design of low-jitter frequency synthesis — LC and/or ring PLL, including loop filter and VCO.
• Own the phase interpolator and phase rotation scheme, including INL/DNL and interpolation resolution.
• Design high-frequency clock distribution across the SerDes macro: buffers, duty-cycle correction, skew control, isolation.
• Define and verify CDR architecture and loop dynamics; model in MATLAB/Python and compare to silicon results.
• Build phase-noise and jitter budgets for the link and identify jitter sources.
• Build verification environment for blocks — PSS/HB, transient analysis, Monte Carlo; provide Verilog-A models.
• Drive layout of blocks in deep sub-micron nodes with attention to inductor and VCO layout and isolation.
• Take blocks through silicon bring-up and bench characterization; correlate measurements to simulations.

Skills

Analog/mixed-signal design

High-speed SerDes

Clocking circuits

Jitter analysis

Silicon bring-up

Education

BS/MS/PhD in Electrical Engineering

Tools

Cadence Virtuoso

Spectre

Monte Carlo/corner analysis

Job description

d-Matrix is seeking a hands-on senior analog/mixed-signal designer to own the clocking subsystem of our high-speed SerDes on the IO chiplet. You will carry designs from specification through silicon characterization, porting clocking blocks to new nodes and collaborating with datapath, DSP, digital, and firmware teams to meet timing, jitter budgets, and calibration.

The role involves owning PLL/LC or ring PLL designs, phase interpolator/rotation, high-frequency clock distribution, CDR loop