STA Lead – ASIC Timing & Sign-off (Equity Eligible)

Google LLC; Sunnyvale (CA); On-site; USD 192,000 - 278,000; Full time

Benefits offered by this job

Equity

Bonus target

Benefits

Job summary

Google LLC in Sunnyvale, CA is seeking a Physical Design Lead focused on Static Timing Analysis to shape the timing closure for high‑performance AI/ML ASICs.

You will own timing constraint creation, margins, and ECOs, develop STA methodologies, and partner with RTL, DFT, and architecture teams to deliver reliable, scalable TPU silicon.

The role requires leading cross-functional timing efforts and influencing design strategies to meet aggressive performance targets.

Qualifications

• Requires at least a bachelor's degree in a related field or equivalent practical experience.
• 10 years in STA with 5 years in technical leadership.
• Experience achieving full-chip timing convergence and working with timing constraints (SDC).
• Experience with TCL for timing analysis, closure, parasitics, noise, or crosstalk.
• Experience with EDA tools such as PrimeTime, Tempus, Timevision, or STAR-RC.

Responsibilities

• Lead timing constraint creation, validation, and ECOs for complex ASICs.
• Drive STA methodology development and timing signoff processes.
• Develop flows around standard STA and parasitic extraction tools and automate where possible.
• Collaborate with RTL design, DFT, and architecture teams to meet cross-functional timing requirements.
• Guide cross-team efforts to ensure successful tape-out and silicon delivery.

Skills

Static Timing Analysis

Technical Leadership

Timing constraints (SDC)

Tcl scripting

EDA tools (PrimeTime/Tempus/Timevision

Education

Bachelor's degree in Electrical Engineering / Computer Engineering / Computer Science or related field

Master's degree (preferred)

Tools

PrimeTime

Tempus

Timevision

STAR-RC

Job description

Google LLC in Sunnyvale, CA is seeking a Physical Design Lead focused on Static Timing Analysis to shape the timing closure for high‑performance AI/ML ASICs.

You will own timing constraint creation, margins, and ECOs, develop STA methodologies, and partner with RTL, DFT, and architecture teams to deliver reliable, scalable TPU silicon.

The role requires leading cross-functional timing efforts and influencing design strategies to meet aggressive performance targets.