Full-Chip STA Engineer: SoC Timing & Signoff Lead

Google; United States; On-site; USD 163,000 - 236,000; Full time

Benefits offered by this job

Equity

Benefits

Job summary

Google is seeking a Static Timing Analysis Engineer to own SoC STA for full-chip designs. Located in Mountain View, CA, you will work with PrimeTime and Tempus, define timing signoff processes, and drive clock-tree implementation to optimize energy, performance, and area.

The role emphasizes mentoring mid-level engineers and delivering high-complexity silicon. Responsibilities include full-chip STA, timing ECOs, and signoff oversight, with compensation including a strong base, 15% bonus target,

Qualifications

• Bachelor's degree in Electrical Engineering or Computer Science, or equivalent practical experience.
• 8 years of technical experience in silicon timing closure and chip integration.
• Experience in one or more static timing tools (e.g., PrimeTime, Tempus).
• Experience with STA signoff constraint authoring for full-chip level, tapeout signoff requirements, checklists, and associated automation.
• Experience delivering silicon.

Responsibilities

• Deliver system-on-chip (SoC) Static Timing Analysis (STA).
• Define SoC timing signoff process corners, derates, uncertainties, and their tradeoffs.
• Drive clock tree jitter and implementation for SoCs to achieve best energy, performance, and area.
• Manage full chip timing constraint validation, timing signoff checklist criteria, perform full chip STA, timing ECO creation, and oversee final timing signoff for SoCs.

Skills

Tcl scripting

Perl scripting

SoC timing

Education

Bachelor's degree in EE/CS

Master's degree (preferred)

Tools

PrimeTime

Tempus

Job description

Google is seeking a Static Timing Analysis Engineer to own SoC STA for full-chip designs. Located in Mountain View, CA, you will work with PrimeTime and Tempus, define timing signoff processes, and drive clock-tree implementation to optimize energy, performance, and area.

The role emphasizes mentoring mid-level engineers and delivering high-complexity silicon. Responsibilities include full-chip STA, timing ECOs, and signoff oversight, with compensation including a strong base, 15% bonus target,